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Oct 24, 2016 at 8:55 comment added Nick Gammon What about the other bits, like ICIE1, OCIE1B, OCIE1A? I understand about the latency, but interrupts should be able to cope with a couple of clock cycles of not being available. There may be a race condition. The interrupt might be triggered already (ie. the flag in the CPU is set) and turning TIMSK1 off might not stop it being handled. You might also need to reset TOV1 (by writing 1 to it in TIFR1) to ensure that doesn't happen. The uncertainty there leads me to think that turning interrupts off globally is the safer course.
Oct 24, 2016 at 8:14 comment added Edgar Bonet Wouldn't it be more efficient to TIMSK1=0; TIFR1=_BV(TOV1); isrCallback=isr; TIMSK1=_BV(TOIE1);? It spares one CPU register and doesn't contribute interrupt latency.
Oct 24, 2016 at 0:04 history answered Nick Gammon CC BY-SA 3.0