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x86-specific random items
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Userspace poking at MSRs
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The kernel may dump a warning message of the format
"msr: Write to unrecognized MSR $MSR_ADDR by $COMM"
where MSR_ADDR and COMM are documented in the table below.
This warning message does not affect the system in any way - it is only
there to gather info which userspace tools are poking at model-specific
registers (MSRs) with the intent to fix them because userspace should
not access MSRs - that's the kernel's job.
Info below has been gathered so far by the kind help of reporters (big
thanks!).
If you find a MSR reported on your system, in the table below, the text
under it should tell you what to do.
If not, please report it to x86@kernel.org.
Thx.
MSR_ADDR COMM
===============================================================================
0x38f (PERF_GLOBAL_CTRL) i7z
0x38d (PERF_FIXED_CTR_CTRL)
No userspace tool should touch those. Tool needs fixing, Authors pinged.
-------------------------------------------------------------------------------
0x150 (MSR_OC_MAILBOX) throttled
0x1a2 (MSR_IA32_TEMPERATURE_TARGET) intel-undervolt
0x610 (MSR_PKG_POWER_LIMIT)
Work ongoing towards converting to sysfs interfaces.
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0x49 perl (spectre-meltdown-checker.sh)
0x10b perl, older x86_energy_perf
$ grep -r . /sys/devices/system/cpu/vulnerabilities/
should give all the information needed to know which CPU vulnerabilities have been
applied. This script is not needed.
When x86_energy_perf causes this warning, then it is most likely caused
by using an old tool supplied by the distro, with a newer kernel. Versions of
the tool carved out from the 5.11 kernel are fixed.
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0xc0010015 python (ZenStates)
0xc0010292
Supposed to fix some freezes on Zen machines but no definitive proof yet.
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0x17f mcelog
Fix is in v5.11:
68299a42f842 ("x86/mce: Enable additional error logging on certain Intel CPUs")
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0xc0010067 k10ctl
Some AMD F10h undervolting, should simply use cpufreq governor. Not needed.
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0x1a4 (MSR_MISC_FEATURE_CONTROL) xmrig
Reportedly disabling hardware prefetchers improves performance for some miners
on some CPUs: https://github.com/xmrig/xmrig/issues/1433#issuecomment-572126184
after pointing at:
https://software.intel.com/content/www/us/en/develop/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors.html
The kernel's resctrl code touches that MSR too so if anything, this needs a
proper kernel interface to sync accesses to those MSRs and the hw pref control.
Also, those bits are different per model so it needs model logic too
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