| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-03-18 | riscv: Fix a comment typo in set_mm_asid() | Chin Yik Ming | 1 | -1/+1 |
| 2024-04-30 | Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements" | Palmer Dabbelt | 1 | -13/+10 |
| 2024-04-30 | Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ... | Palmer Dabbelt | 1 | -8/+11 |
| 2024-04-29 | riscv: mm: Preserve global TLB entries when switching contexts | Samuel Holland | 1 | -1/+1 |
| 2024-04-29 | riscv: mm: Make asid_bits a local variable | Samuel Holland | 1 | -2/+1 |
| 2024-04-29 | riscv: mm: Use a fixed layout for the MM context ID | Samuel Holland | 1 | -4/+2 |
| 2024-04-29 | riscv: mm: Introduce cntx2asid/cntx2version helper macros | Samuel Holland | 1 | -6/+6 |
| 2024-04-18 | riscv: Include riscv_set_icache_flush_ctx prctl | Charlie Jenkins | 1 | -8/+11 |
| 2024-02-15 | membarrier: riscv: Add full memory barrier in switch_mm() | Andrea Parri | 1 | -0/+2 |
| 2023-08-31 | riscv: mm: use bitmap_zero() API | Ye Xingchen | 1 | -1/+1 |
| 2023-03-21 | riscv: mm: Fix incorrect ASID argument when flushing TLB | Dylan Jhong | 1 | -1/+1 |
| 2023-03-09 | riscv: asid: Fixup stale TLB entry cause application crash | Guo Ren | 1 | -10/+20 |
| 2023-03-09 | Revert "riscv: mm: notify remote harts about mmu cache updates" | Sergey Matyukevich | 1 | -10/+0 |
| 2022-12-08 | riscv: mm: notify remote harts about mmu cache updates | Sergey Matyukevich | 1 | -0/+10 |
| 2022-01-19 | riscv: Implement sv48 support | Alexandre Ghiti | 1 | -2/+2 |
| 2021-10-04 | riscv: mm: don't advertise 1 num_asid for 0 asid bits | Vineet Gupta | 1 | -3/+5 |
| 2021-06-30 | riscv: add ASID-based tlbflushing methods | Guo Ren | 1 | -1/+1 |
| 2021-06-08 | riscv: mm: Use better bitmap_zalloc() | Kefeng Wang | 1 | -2/+1 |
| 2021-05-29 | riscv: Add __init section marker to some functions again | Jisheng Zhang | 1 | -1/+1 |
| 2021-05-25 | riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred() | Jisheng Zhang | 1 | -3/+4 |
| 2021-02-18 | RISC-V: Implement ASID allocator | Anup Patel | 1 | -4/+261 |
| 2019-11-17 | riscv: add nommu support | Christoph Hellwig | 1 | -0/+2 |
| 2019-10-28 | riscv: add missing header file includes | Paul Walmsley | 1 | -0/+1 |
| 2019-08-30 | riscv: Using CSR numbers to access CSRs | Bin Meng | 1 | -6/+1 |
| 2019-05-16 | riscv: move switch_mm to its own file | Gary Guo | 1 | -0/+69 |
