| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-01-09 | riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW | Jisheng Zhang | 1 | -0/+31 |
| 2022-02-08 | riscv: extable: fix err reg writing in dedicated uaccess handler | Jisheng Zhang | 1 | -3/+3 |
| 2022-01-05 | riscv: extable: add a dedicated uaccess handler | Jisheng Zhang | 1 | -0/+27 |
| 2022-01-05 | riscv: extable: add `type` and `data` fields | Jisheng Zhang | 1 | -4/+21 |
| 2022-01-05 | riscv: extable: use `ex` for `exception_table_entry` | Jisheng Zhang | 1 | -5/+5 |
| 2022-01-05 | riscv: extable: make fixup_exception() return bool | Jisheng Zhang | 1 | -3/+3 |
| 2022-01-05 | riscv: bpf: move rv_bpf_fixup_exception signature to extable.h | Jisheng Zhang | 1 | -6/+0 |
| 2022-01-05 | riscv: switch to relative exception tables | Jisheng Zhang | 1 | -1/+1 |
| 2021-11-05 | riscv, bpf: Fix RV32 broken build, and silence RV64 warning | Björn Töpel | 1 | -2/+2 |
| 2021-10-28 | riscv, bpf: Add BPF exception tables | Tong Tiangen | 1 | -5/+14 |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig | 1 | -2/+2 |
| 2019-05-24 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120 | Thomas Gleixner | 1 | -14/+1 |
| 2017-09-26 | RISC-V: ELF and module implementation | Palmer Dabbelt | 1 | -0/+37 |
