| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-09-04 | clk: amlogic: introduce a common pclk definition | Jerome Brunet | 1 | -9/+17 |
| 2025-09-04 | clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED | Jerome Brunet | 1 | -89/+99 |
| 2025-09-04 | clk: amlogic: drop meson-clkcee | Jerome Brunet | 1 | -4/+4 |
| 2025-08-25 | clk: amlogic: naming consistency alignment | Jerome Brunet | 1 | -291/+288 |
| 2025-07-29 | Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' ... | Stephen Boyd | 1 | -394/+98 |
| 2025-07-26 | clk: Fix typos | Bjorn Helgaas | 1 | -1/+1 |
| 2025-07-02 | clk: amlogic: drop clk_regmap tables | Jerome Brunet | 1 | -393/+0 |
| 2025-06-30 | clk: amlogic: remove unnecessary headers | Jerome Brunet | 1 | -1/+98 |
| 2025-03-14 | clk: amlogic: gxbb: drop non existing 32k clock parent | Jerome Brunet | 1 | -6/+6 |
| 2025-03-14 | clk: amlogic: gxbb: drop incorrect flag on 32k clock | Jerome Brunet | 1 | -1/+1 |
| 2024-12-02 | module: Convert symbol namespace to string literal | Peter Zijlstra | 1 | -1/+1 |
| 2024-09-30 | clk: meson: mpll: Delete a useless spinlock from the MPLL | Chuan Liu | 1 | -6/+0 |
| 2024-07-29 | clk: meson: introduce symbol namespace for amlogic clocks | Jerome Brunet | 1 | -0/+1 |
| 2024-06-14 | clk: meson: add missing MODULE_DESCRIPTION() macros | Jerome Brunet | 1 | -1/+2 |
| 2024-04-10 | clk: meson: fix module license to GPL only | Neil Armstrong | 1 | -1/+1 |
| 2023-08-30 | Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ... | Stephen Boyd | 1 | -424/+424 |
| 2023-08-08 | clk: meson: eeclk: move bindings include to main driver | Neil Armstrong | 1 | -0/+2 |
| 2023-08-08 | clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS | Neil Armstrong | 1 | -424/+422 |
| 2023-07-19 | clk: Explicitly include correct DT includes | Rob Herring | 1 | -1/+1 |
| 2021-11-30 | clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB | Martin Blumenstingl | 1 | -3/+41 |
| 2020-11-23 | clk: meson: enable building as modules | Kevin Hilman | 1 | -1/+4 |
| 2020-04-16 | clk: meson: gxbb: Prepare the GPU clock tree to change at runtime | Martin Blumenstingl | 1 | -18/+22 |
| 2020-02-13 | clk: meson: gxbb: set audio output clock hierarchy | Jerome Brunet | 1 | -8/+10 |
| 2020-02-13 | clk: meson: gxbb: add the gxl internal dac gate | Jerome Brunet | 1 | -0/+3 |
| 2019-10-01 | clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate | Martin Blumenstingl | 1 | -0/+1 |
| 2019-07-29 | clk: meson: clk-regmap: migrate to new parent description method | Alexandre Mergnat | 1 | -0/+3 |
| 2019-07-29 | clk: meson: gxbb: migrate to the new parent description method | Alexandre Mergnat | 1 | -203/+451 |
| 2019-05-20 | clk: meson: gxbb: no spread spectrum on mpll0 | Jerome Brunet | 1 | -5/+0 |
| 2019-03-19 | clk: meson-gxbb: round the vdec dividers to closest | Maxime Jourdan | 1 | -0/+2 |
| 2019-02-04 | clk: meson: factorise meson64 peripheral clock controller drivers | Jerome Brunet | 1 | -75/+197 |
| 2019-02-02 | clk: meson: rework and clean drivers dependencies | Jerome Brunet | 1 | -1/+4 |
| 2019-01-18 | clk: meson: gxbb: claim clock controller input clock from DT | Jerome Brunet | 1 | -13/+24 |
| 2018-12-14 | Merge branch 'clk-fixes' into clk-next | Stephen Boyd | 1 | -0/+12 |
| 2018-12-13 | Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl... | Stephen Boyd | 1 | -1/+7 |
| 2018-12-03 | clk: meson: Mark some things static | Stephen Boyd | 1 | -4/+4 |
| 2018-11-27 | clk: meson: Fix GXL HDMI PLL fractional bits width | Neil Armstrong | 1 | -1/+7 |
| 2018-11-23 | clk: meson-gxbb: Add video clocks | Neil Armstrong | 1 | -0/+722 |
| 2018-11-23 | clk: meson-gxbb: Fix HDMI PLL for GXL SoCs | Neil Armstrong | 1 | -2/+49 |
| 2018-11-08 | clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL | Christian Hewitt | 1 | -0/+12 |
| 2018-09-26 | clk: meson: clk-pll: drop hard-coded rates from pll tables | Jerome Brunet | 1 | -60/+60 |
| 2018-09-26 | clk: meson: clk-pll: remove od parameters | Jerome Brunet | 1 | -256/+228 |
| 2018-09-26 | clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary | Jerome Brunet | 1 | -4/+8 |
| 2018-09-26 | clk: meson: clk-pll: add enable bit | Jerome Brunet | 1 | -2/+30 |
| 2018-07-09 | clk: meson: add gen_clk | Jerome Brunet | 1 | -0/+66 |
| 2018-07-09 | clk: meson: stop rate propagation for audio clocks | Jerome Brunet | 1 | -9/+7 |
| 2018-07-09 | clk: meson: remove obsolete register access | Jerome Brunet | 1 | -34/+2 |
| 2018-06-19 | clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL | Neil Armstrong | 1 | -0/+1 |
| 2018-05-18 | clk: meson: use SPDX license identifiers consistently | Jerome Brunet | 1 | -14/+1 |
| 2018-05-15 | clk: meson: gxbb: add the video decoder clocks | Maxime Jourdan | 1 | -0/+114 |
| 2018-03-14 | clk: meson: Drop unused local variable and add static | Stephen Boyd | 1 | -2/+2 |
| 2018-03-13 | clk: meson: clean-up clk81 clocks | Jerome Brunet | 1 | -4/+2 |
| 2018-03-13 | clk: meson: add fdiv clock gates | Jerome Brunet | 1 | -10/+90 |
| 2018-03-13 | clk: meson: add mpll pre-divider | Jerome Brunet | 1 | -3/+20 |
| 2018-03-13 | clk: meson: add gp0 frac parameter for axg and gxl | Jerome Brunet | 1 | -1/+6 |
| 2018-03-13 | clk: meson: remove special gp0 lock loop | Jerome Brunet | 1 | -1/+0 |
| 2018-03-13 | clk: meson: poke pll CNTL last | Jerome Brunet | 1 | -2/+2 |
| 2018-03-13 | clk: meson: use hhi syscon if available | Jerome Brunet | 1 | -11/+28 |
| 2018-03-13 | clk: meson: split divider and gate part of mpll | Jerome Brunet | 1 | -21/+57 |
| 2018-03-13 | clk: meson: migrate plls clocks to clk_regmap | Jerome Brunet | 1 | -185/+239 |
| 2018-03-13 | clk: meson: migrate the audio divider clock to clk_regmap | Jerome Brunet | 1 | -21/+9 |
| 2018-03-13 | clk: meson: migrate mplls clocks to clk_regmap | Jerome Brunet | 1 | -84/+77 |
| 2018-03-13 | clk: meson: migrate muxes to clk_regmap | Jerome Brunet | 1 | -160/+150 |
| 2018-03-13 | clk: meson: migrate dividers to clk_regmap | Jerome Brunet | 1 | -109/+108 |
| 2018-03-13 | clk: meson: migrate gates to clk_regmap | Jerome Brunet | 1 | -129/+137 |
| 2018-03-13 | clk: meson: add regmap to the clock controllers | Jerome Brunet | 1 | -10/+23 |
| 2018-03-13 | clk: meson: remove obsolete comments | Jerome Brunet | 1 | -6/+0 |
| 2018-03-13 | clk: meson: only one loop index is necessary in probe | Jerome Brunet | 1 | -7/+6 |
| 2018-03-13 | clk: meson: use devm_of_clk_add_hw_provider | Jerome Brunet | 1 | -2/+3 |
| 2018-03-13 | clk: meson: use dev pointer where possible | Jerome Brunet | 1 | -1/+1 |
| 2018-02-12 | clk: meson: gxbb: add the fractional part of the fixed_pll | Jerome Brunet | 1 | -0/+5 |
| 2018-02-12 | clk: meson: fix rate calculation of plls with a fractional part | Jerome Brunet | 1 | -1/+13 |
| 2018-02-12 | clk: meson: add the gxl hdmi pll | Jerome Brunet | 1 | -2/+48 |
| 2018-02-12 | clk: meson: add od3 to the pll driver | Jerome Brunet | 1 | -0/+5 |
| 2018-02-12 | clk: meson: remove useless pll rate params tables | Jerome Brunet | 1 | -94/+0 |
| 2017-12-14 | clk: meson: make the spinlock naming more specific | Yixun Lan | 1 | -56/+56 |
| 2017-12-08 | clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks | Jerome Brunet | 1 | -13/+3 |
| 2017-11-27 | clk: meson: gxbb: fix wrong clock for SARADC/SANA | Yixun Lan | 1 | -2/+2 |
| 2017-10-20 | clk: meson: gxbb: Add VPU and VAPB clocks data | Neil Armstrong | 1 | -0/+292 |
| 2017-08-23 | Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl... | Stephen Boyd | 1 | -4/+185 |
| 2017-08-04 | clk: meson: gxbb: Add sd_emmc clk0 clocks | Jerome Brunet | 1 | -0/+177 |
| 2017-08-04 | clk: meson: gxbb: fix clk_mclk_i958 divider flags | Jerome Brunet | 1 | -3/+4 |
| 2017-08-04 | clk: meson: gxbb: fix meson cts_amclk divider flags | Jerome Brunet | 1 | -1/+2 |
| 2017-08-04 | clk: meson: gxbb: fix protection against undefined clks | Jerome Brunet | 1 | -0/+2 |
| 2017-08-01 | clk: meson: mpll: fix mpll0 fractional part ignored | Jerome Brunet | 1 | -0/+5 |
| 2017-06-16 | Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ... | Stephen Boyd | 1 | -5/+8 |
| 2017-06-16 | clk: meson: gxbb: add all clk81 parents | Jerome Brunet | 1 | -5/+8 |
| 2017-06-02 | clk: meson-gxbb: Add const to some parent name arrays | Stephen Boyd | 1 | -3/+3 |
| 2017-05-29 | clk: meson-gxbb: Add EE 32K Clock for CEC | Neil Armstrong | 1 | -0/+54 |
| 2017-05-29 | clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 | Jerome Brunet | 1 | -1/+1 |
| 2017-05-29 | clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver | Martin Blumenstingl | 1 | -61/+3 |
| 2017-04-07 | clk: meson: gxbb: add cts_i958 clock | Jerome Brunet | 1 | -0/+21 |
| 2017-04-07 | clk: meson: gxbb: add cts_mclk_i958 | Jerome Brunet | 1 | -0/+52 |
| 2017-04-07 | clk: meson: gxbb: add cts_amclk | Jerome Brunet | 1 | -0/+67 |
| 2017-04-07 | clk: meson: gxbb: protect against holes in the onecell_data array | Jerome Brunet | 1 | -0/+4 |
| 2017-04-04 | clk: meson-gxbb: Add GXL/GXM GP0 Variant | Neil Armstrong | 1 | -28/+273 |
| 2017-04-04 | clk: meson-gxbb: Add GP0 PLL init parameters | Neil Armstrong | 1 | -0/+13 |
| 2017-04-04 | clk: meson-gxbb: Add MALI clocks | Neil Armstrong | 1 | -0/+139 |
| 2017-03-27 | clk: meson: gxbb: mpll: use rw operation | Jerome Brunet | 1 | -3/+3 |
| 2017-03-27 | clk: meson: mpll: add rw operation | Jerome Brunet | 1 | -0/+30 |
| 2017-03-27 | clk: gxbb: put dividers and muxes in tables | Jerome Brunet | 1 | -8/+20 |
| 2017-03-27 | clk: meson: add missing const qualifiers on gate arrays | Jerome Brunet | 1 | -1/+1 |
| 2017-01-23 | clk: gxbb: add the SAR ADC clocks and expose them | Martin Blumenstingl | 1 | -0/+48 |
| 2016-09-02 | Merge branch 'clk-meson-gxbb' into clk-next | Michael Turquette | 1 | -84/+84 |
| 2016-09-01 | gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b | Alexander Müller | 1 | -84/+84 |
| 2016-08-15 | Merge branch 'clk-meson-gxbb' into clk-next | Stephen Boyd | 1 | -0/+9 |
| 2016-08-15 | clk: gxbb: add MMC gate clocks, and expose for DT | Kevin Hilman | 1 | -0/+9 |
| 2016-08-15 | clk: gxbb: use builtin_platform_driver to simplify the code | Wei Yongjun | 1 | -5/+1 |
| 2016-07-06 | clk: meson: make gxbb explicitly non-modular | Paul Gortmaker | 1 | -14/+4 |
| 2016-06-22 | clk: gxbb: add AmLogic GXBB clk controller driver | Michael Turquette | 1 | -0/+954 |
