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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This is entirely SoC clk drivers.
The majority diff wise is for the new Rockchip and Qualcomm clk
drivers which is mostly lines and lines of data structures to describe
the clk hardware in these SoCs. Beyond those two, Renesas continues to
incrementally add clks to their SoC drivers, causing them to show up
higher in the diffstat this time because they added quite a few clks
all over the place.
Overall it is a semi-quiet release that has some new clk drivers and
the usual fixes for clock data that was wrong or missing and
non-critical cleanups that plug error paths or fix typos.
New Drivers:
- Qualcomm IPQ5424 Network Subsystem Clock Controller
- Qualcomm SM8750 Video Clock Controller
- Rockchip RV1126B and RK3506 clock drivers
- i.MX8ULP SIM LPAV clock driver
- Samsung ACPM (firmware interface) clock driver
- Altera Agilex5 clock driver"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (117 commits)
clk: keystone: fix compile testing
clk: keystone: syscon-clk: fix regmap leak on probe failure
clk: qcom: Mark camcc_sm7150_hws static
clk: samsung: exynos-clkout: Assign .num before accessing .hws
clk: rockchip: Add clock and reset driver for RK3506
dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
clk: actions: Fix discarding const qualifier by 'container_of' macro
clk: spacemit: Set clk_hw_onecell_data::num before using flex array
clk: visconti: Add VIIF clocks
dt-bindings: clock: tmpv770x: Add VIIF clocks
dt-bindings: clock: tmpv770x: Remove definition of number of clocks
clk: visconti: Do not define number of clocks in bindings
clk: rockchip: Add clock controller for the RV1126B
dt-bindings: clock, reset: Add support for rv1126b
clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
clk: qcom: x1e80100-dispcc: Add USB4 router link resets
dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
dt-bindings: clock: qcom: Add SM8750 video clock controller
clk: qcom: branch: Extend invert logic for branch2 mem clocks
...
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc/IIO driver updates from Greg KH:
"Here is the big set of char/misc/iio driver updates for 6.19-rc1. Lots
of stuff in here including:
- lots of IIO driver updates, cleanups, and additions
- large interconnect driver changes as they get converted over to a
dynamic system of ids
- coresight driver updates
- mwave driver updates
- binder driver updates and changes
- comedi driver fixes now that the fuzzers are being set loose on
them
- nvmem driver updates
- new uio driver addition
- lots of other small char/misc driver updates, full details in the
shortlog
All of these have been in linux-next for a while now"
* tag 'char-misc-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (304 commits)
char: applicom: fix NULL pointer dereference in ac_ioctl
hangcheck-timer: fix coding style spacing
hangcheck-timer: Replace %Ld with %lld
hangcheck-timer: replace printk(KERN_CRIT) with pr_crit
uio: Add SVA support for PCI devices via uio_pci_generic_sva.c
dt-bindings: slimbus: fix warning from example
intel_th: Fix error handling in intel_th_output_open
misc: rp1: Fix an error handling path in rp1_probe()
char: xillybus: add WQ_UNBOUND to alloc_workqueue users
misc: bh1770glc: use pm_runtime_resume_and_get() in power_state_store
misc: cb710: Fix a NULL vs IS_ERR() check in probe()
mux: mmio: Add suspend and resume support
virt: acrn: split acrn_mmio_dev_res out of acrn_mmiodev
greybus: gb-beagleplay: Fix timeout handling in bootloader functions
greybus: add WQ_PERCPU to alloc_workqueue users
char/mwave: drop typedefs
char/mwave: drop printk wrapper
char/mwave: remove printk tracing
char/mwave: remove unneeded fops
char/mwave: remove MWAVE_FUTZ_WITH_OTHER_DEVICES ifdeffery
...
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git://www.linux-watchdog.org/linux-watchdog
Pull watchdog updates from Wim Van Sebroeck:
- Add watchdog support for:
- Renesas WWDT
- AST2700 platform
- MediaTek MT8189 SoC
- Loongson-2k0300 watchdog
- Qualcomm Kaanapali watchdog
- RK3506 compatible
- Airoha AN7583 SoC
- DT Schema conversions:
- lantiq,wdt
- TI OMAP
- marvell,orion-wdt
- Several other fixes and improvements
* tag 'linux-watchdog-6.19-rc1' of git://www.linux-watchdog.org/linux-watchdog: (30 commits)
watchdog: starfive: Fix resource leak in probe error path
dt-bindings: watchdog: airoha: Add support for Airoha AN7583 SoC
dt-bindings: watchdog: lantiq,wdt: convert bindings to dtschema
dt-bindings: watchdog: Add RK3506 compatible
dt-bindings: watchdog: Document Qualcomm Kaanapali watchdog
watchdog: wdat_wdt: Fix ACPI table leak in probe function
watchdog: loongson1: Add Loongson-2k0300 watchdog support
dt-bindings: watchdog: loongson,ls1x-wdt: Add ls2k0300-wdt compatible
watchdog: loongson1: Drop CONFIG_OF
watchdog: loongson1: Simplify ls1x_wdt_probe code
watchdog: loongson1: Add missing MODULE_PARM_DESC
watchdog/diag288: Fix module comment typos
dt-bindings: watchdog: Support MediaTek MT8189 wdt
dt-bindings: watchdog: mediatek,mtk-wdt: Add compatible for MT8189 SoC
dt-bindings: mfd: rohm,bd96801-pmic: Correct timeout-sec length and reference watchdog schema
dt-bindings: watchdog: Allow node names named 'pmic'
dt-bindings: watchdog: Restrict timeout-sec to one number
watchdog: renesas_wwdt: add driver
dt-bindings: watchdog: Add Renesas WWDT
dt-bindings: watchdog: Convert marvell,orion-wdt to DT schema
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"This is the first half of the driver changes:
- A treewide interface change to the "syscore" operations for power
management, as a preparation for future Tegra specific changes
- Reset controller updates with added drivers for LAN969x, eic770 and
RZ/G3S SoCs
- Protection of system controller registers on Renesas and Google
SoCs, to prevent trivially triggering a system crash from e.g.
debugfs access
- soc_device identification updates on Nvidia, Exynos and Mediatek
- debugfs support in the ST STM32 firewall driver
- Minor updates for SoC drivers on AMD/Xilinx, Renesas, Allwinner, TI
- Cleanups for memory controller support on Nvidia and Renesas"
* tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (114 commits)
memory: tegra186-emc: Fix missing put_bpmp
Documentation: reset: Remove reset_controller_add_lookup()
reset: fix BIT macro reference
reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
reset: th1520: Support reset controllers in more subsystems
reset: th1520: Prepare for supporting multiple controllers
dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
reset: remove legacy reset lookup code
clk: davinci: psc: drop unused reset lookup
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: eswin: Add eic7700 reset driver
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: sparx5: add LAN969x support
dt-bindings: reset: microchip: Add LAN969x support
soc: rockchip: grf: Add select correct PWM implementation on RK3368
soc/tegra: pmc: Add USB wake events for Tegra234
amba: tegra-ahb: Fix device leak on SMMU enable
...
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Pull SoC devicetree updates from Arnd Bergmann:
"Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive
SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the
currently highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs,
this one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip
based on Cortex-A53, and closely related to MSM8917 (Snapdragn
425), which we already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree,
with the majority of the changes going into the Qualcomm, NXP, Renesas
and Rockchips platforms"
* tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits)
arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1
ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend
arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
arm64: dts: Add gpio_intc node for Amlogic S7D SoCs
arm64: dts: Add gpio_intc node for Amlogic S7 SoCs
arm64: dts: Add gpio_intc node for Amlogic S6 SoCs
arm64: dts: amlogic: s7d: add ao secure node
arm64: dts: amlogic: s7: add ao secure node
arm64: dts: amlogic: s6: add ao secure node
arm64: dts: amlogic: Fix the register name of the 'DBI' region
dts: arm64: amlogic: add a5 pinctrl node
arm64: dts: amlogic: s7d: add power domain controller node
arm64: dts: amlogic: s7: add power domain controller node
arm64: dts: amlogic: s6: add power domain controller node
dts: arm64: amlogic: Add ISP related nodes for C3
arm64: dts: meson: add initial device-tree for Tanix TX9 Pro
dt-bindings: arm: amlogic: add support for Tanix TX9 Pro
...
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git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
Pull iommu updates from Joerg Roedel:
- Introduction of the generic IO page-table framework with support for
Intel and AMD IOMMU formats from Jason.
This has good potential for unifying more IO page-table
implementations and making future enhancements more easy. But this
also needed quite some fixes during development. All known issues
have been fixed, but my feeling is that there is a higher potential
than usual that more might be needed.
- Intel VT-d updates:
- Use right invalidation hint in qi_desc_iotlb()
- Reduce the scope of INTEL_IOMMU_FLOPPY_WA
- ARM-SMMU updates:
- Qualcomm device-tree binding updates for Kaanapali and Glymur SoCs
and a new clock for the TBU.
- Fix error handling if level 1 CD table allocation fails.
- Permit more than the architectural maximum number of SMRs for
funky Qualcomm mis-implementations of SMMUv2.
- Mediatek driver:
- MT8189 iommu support
- Move ARM IO-pgtable selftests to kunit
- Device leak fixes for a couple of drivers
- Random smaller fixes and improvements
* tag 'iommu-updates-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (81 commits)
iommupt/vtd: Support mgaw's less than a 4 level walk for first stage
iommupt/vtd: Allow VT-d to have a larger table top than the vasz requires
powerpc/pseries/svm: Make mem_encrypt.h self contained
genpt: Make GENERIC_PT invisible
iommupt: Avoid a compiler bug with sw_bit
iommu/arm-smmu-qcom: Enable use of all SMR groups when running bare-metal
iommupt: Fix unlikely flows in increase_top()
iommu/amd: Propagate the error code returned by __modify_irte_ga() in modify_irte_ga()
MAINTAINERS: Update my email address
iommu/arm-smmu-v3: Fix error check in arm_smmu_alloc_cd_tables
dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
iommu/vt-d: Restore previous domain::aperture_end calculation
iommu/vt-d: Fix unused invalidation hint in qi_desc_iotlb
iommu/vt-d: Set INTEL_IOMMU_FLOPPY_WA depend on BLK_DEV_FD
iommu/tegra: fix device leak on probe_device()
iommu/sun50i: fix device leak on of_xlate()
iommu/omap: simplify probe_device() error handling
iommu/omap: fix device leaks on probe_device()
iommu/mediatek-v1: add missing larb count sanity check
iommu/mediatek-v1: fix device leaks on probe()
...
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git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
"pmdomain core:
- Allow power-off for out-of-band wakeup-capable devices
- Drop the redundant call to dev_pm_domain_detach() for the amba bus
- Extend the genpd governor for CPUs to account for IPIs
pmdomain providers:
- bcm: Add support for BCM2712
- mediatek: Add support for MFlexGraphics power domains
- mediatek: Add support for MT8196 power domains
- qcom: Add RPMh power domain support for Kaanapali
- rockchip: Add support for RV1126B
pmdomain consumers:
- usb: dwc3: Enable out of band wakeup for i.MX95
- usb: chipidea: Enable out of band wakeup for i.MX95"
* tag 'pmdomain-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (26 commits)
pmdomain: Extend the genpd governor for CPUs to account for IPIs
smp: Introduce a helper function to check for pending IPIs
pmdomain: mediatek: convert from clk round_rate() to determine_rate()
amba: bus: Drop dev_pm_domain_detach() call
pmdomain: bcm: bcm2835-power: Prepare to support BCM2712
pmdomain: mediatek: mtk-mfg: select MAILBOX in Kconfig
pmdomain: mediatek: Add support for MFlexGraphics
pmdomain: mediatek: Fix build-errors
cpuidle: psci: Replace deprecated strcpy in psci_idle_init_cpu
pmdomain: rockchip: Add support for RV1126B
pmdomain: mediatek: Add support for MT8196 HFRPSYS power domains
pmdomain: mediatek: Add support for MT8196 SCPSYS power domains
pmdomain: mediatek: Add support for secure HWCCF infra power on
pmdomain: mediatek: Add support for Hardware Voter power domains
pmdomain: qcom: rpmhpd: Add RPMh power domain support for Kaanapali
usb: dwc3: imx8mp: Set out of band wakeup for i.MX95
usb: chipidea: ci_hdrc_imx: Set out of band wakeup for i.MX95
usb: chipidea: core: detach power domain for ci_hdrc platform device
pmdomain: core: Allow power-off for out-of-band wakeup-capable devices
PM: wakeup: Add out-of-band system wakeup support for devices
...
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and 'clk-qcom' into clk-next
* clk-visconti:
clk: visconti: Add VIIF clocks
dt-bindings: clock: tmpv770x: Add VIIF clocks
dt-bindings: clock: tmpv770x: Remove definition of number of clocks
clk: visconti: Do not define number of clocks in bindings
* clk-imx:
clk: imx: add driver for imx8ulp's sim lpav
dt-bindings: clock: document 8ULP's SIM LPAV
clk: imx: imx8mp-audiomix: use devm_auxiliary_device_create() to simple code
clk: imx: Add some delay before deassert the reset
* clk-microchip:
reset: mpfs: add non-auxiliary bus probing
clk: lan966x: remove unused dt-bindings include
clk: microchip: mpfs: use regmap for clocks
dt-bindings: clk: microchip: mpfs: remove first reg region
* clk-rockchip:
clk: rockchip: Add clock and reset driver for RK3506
dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
clk: rockchip: Add clock controller for the RV1126B
dt-bindings: clock, reset: Add support for rv1126b
clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
dt-bindings: clock: rk3568: Drop CLK_NR_CLKS define
clk: rockchip: rk3568: Drop CLK_NR_CLKS usage
dt-bindings: clock: rk3568: Add SCMI clock ids
* clk-qcom: (48 commits)
clk: qcom: Mark camcc_sm7150_hws static
clk: qcom: x1e80100-dispcc: Add USB4 router link resets
dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
dt-bindings: clock: qcom: Add SM8750 video clock controller
clk: qcom: branch: Extend invert logic for branch2 mem clocks
clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch
clk: qcom: clk_mem_branch: add enable mask and invert flags
clk: qcom: mmcc-sdm660: Add missing MDSS reset
dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset
clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers
clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure
dt-bindings: clock: qcom: Add Kaanapali Global clock controller
dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali
clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops
clk: qcom: camcc-sm7150: Fix PLL config of PLL2
clk: qcom: camcc-sm6350: Fix PLL config of PLL2
clk: qcom: Add NSS clock controller driver for IPQ5424
...
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and 'clk-mediatek' into clk-next
* clk-socfpga:
clk: socfpga: agilex5: add clock driver for Agilex5
* clk-renesas: (35 commits)
clk: renesas: r9a09g077: Add SPI module clocks
clk: renesas: r9a09g056: Add USB3.0 clocks/resets
clk: renesas: r9a09g057: Add USB3.0 clocks/resets
clk: renesas: r9a09g047: Add RSCI clocks/resets
dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks
dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks
clk: renesas: r9a06g032: Fix memory leak in error path
clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration
clk: renesas: r9a09g077: Remove stray blank line
clk: renesas: r9a09g077: Propagate rate changes to parent clocks
clk: renesas: r8a779a0: Add 3DGE module clock
clk: renesas: r8a779a0: Add ZG Core clock
clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB
dt-bindings: clock: r8a779a0: Add ZG core clock
clk: renesas: r9a09g056: Add clock and reset entries for ISP
clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets
clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules
clk: renesas: r9a09g077: Add TSU module clock
clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC
clk: renesas: rzv2h: Add support for DSI clocks
...
* clk-cleanup:
clk: keystone: fix compile testing
clk: keystone: syscon-clk: fix regmap leak on probe failure
clk: samsung: exynos-clkout: Assign .num before accessing .hws
clk: actions: Fix discarding const qualifier by 'container_of' macro
clk: spacemit: Set clk_hw_onecell_data::num before using flex array
clk: spacemit: fix comment typo
clk: keystone: Fix discarded const qualifiers
clk: sprd: sc9860: Simplify with of_device_get_match_data()
* clk-samsung:
firmware: exynos-acpm: add empty method to allow compile test
MAINTAINERS: add ACPM clock bindings and driver
clk: samsung: add Exynos ACPM clock driver
firmware: exynos-acpm: register ACPM clocks pdev
firmware: exynos-acpm: add DVFS protocol
dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks
clk: samsung: clk-pll: simplify samsung_pll_lock_wait()
clk: samsung: exynosautov920: add block mfc clock support
clk: samsung: exynosautov920: add clock support
dt-bindings: clock: exynosautov920: add mfc clock definitions
dt-bindings: clock: exynosautov920: add m2m clock definitions
dt-bindings: clock: google,gs101-clock: add power-domains
* clk-mediatek:
clk: en7523: Add reset-controller support for EN7523 SoC
dt-bindings: clock: airoha: Add reset support to EN7523 clock binding
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soc/drivers
Reset controller updates for v6.19
* Add support for LAN969x, eic770 and RZ/G3S reset controllers,
for the RZ/G3S USB-PHY reset controller, and for the remaining
TH1520 reset controllers.
* Drop legacy reset control lookup code.
* Include linux/bits.h from linux/reset.h to make it self-contained.
* tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux:
Documentation: reset: Remove reset_controller_add_lookup()
reset: fix BIT macro reference
reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
reset: th1520: Support reset controllers in more subsystems
reset: th1520: Prepare for supporting multiple controllers
dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
reset: remove legacy reset lookup code
clk: davinci: psc: drop unused reset lookup
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: eswin: Add eic7700 reset driver
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: sparx5: add LAN969x support
dt-bindings: reset: microchip: Add LAN969x support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add device tree bindings for clock and reset unit on RK3506 SoC.
Add clock and reset IDs for RK3506 SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251121075350.2564860-2-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: 9Tripod X3568, 100ASK DShanPi A1, LinkEase EasePi R1,
FriendlyElec NanoPi R76S
Interesting archeological addition: RK3368 (2015) gets display
output afterall.
New peripherals: vicap on px30 and rk356x, PCIe Gen2x1 on RK3528,
use actual clock-ids for SCMI clocks - not hardcoded numbers,
CQE support for the eMMC on RK3588.
As well as a number of enablements for individual boards.
For example enablement for the now usable NPU.
* tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (43 commits)
arm64: dts: rockchip: add vicap node to rk356x
arm64: dts: rockchip: add the vip node to px30
arm64: dts: rockchip: fixes audio for 100ASK DshanPi A1
arm64: dts: rockchip: fixes vcc3v3_s0 supply for 100ASK DshanPi A1
arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1
arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1
arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boards
arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4
arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid Nova
arm64: dts: rockchip: add eMMC CQE support for rk3588
arm64: dts: rockchip: enable HDMI audio on Rock 5 ITX
arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3C
arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5A
arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5A
arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356x
arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 board
arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5T
arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5C
arm64: dts: rockchip: Add devicetree for the 9Tripod X3568 v4
dt-bindings: arm: rockchip: Add 9Tripod X3568 series
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.19
Introduce support for the Redxa Dragon Q6A development board, the Huawei
MateBoot E 2019, the Asus ZenFone 2 Laser/Selfie, the MSM8937 platform
and the Xiaomo Redmi 3S device based on it.
SoC dtsi files for Agatti, Hamoa, Kodiak, Monaco, Purwa, and Talos, are
renamed in order to better facilitate the addition of new boards on the
various SKUs of these.
Cooling maps are introduced for the CPU cores in IPQ5424, and the
network subsystem clock controller is added.
On Lemans, RTC is enabled, the EVK fan controller is described and a
camera mezzanine overlay is introduced.
Touchscreen support is added to the BQ Aquaris M5, and the touchscreen
from Samsung Galaxy Core Prime is moved to the common platform to
benefit the other devices sharing common definitions.
On Agatti two more UARTs are described, as well as APR and the related audio
services, and the LPASS LPI pin controller. The RB1 board gets HDMI
autio playback support.
On Kodiak-based targets, Fairphone FP5 gains definitions of the UW camera
actuator, regulator for the ToF sensor, and haptic module. The SHIFT
SHIFTphone 8 gains RGB and flash LEDs, and Venus support. The Rb3Gen2
development board gets QUP firmware path defined, to support dynamic
loading of the serial engine firmware. Kodiak also gains Coresight
devices for AOSS and QDSS blocks.
Display support is added for the Talos platform, and enabled on the Ride
board. Talos also gains the definitions to scale DDR and L3
interconnects.
On SC8280XP, the camera privacy indicator on Lenovo Thinkpad X13s is
connected to the camera stack. Off-by-one GPI DMA channels are
corrected.
The SDM845-based LG and OnePlus custom defined rmtfs guard pages are
replaced with the inline-support for guard pages.
SDX75 DWC3 node is flattened and marked for USB role switching.
On SM8550, the camera subsystem and the S5K3M5 camera sensor is
introduced for the QRD, and an overlay for the "Rear Camera Card" for
the Hardware Development Kit (HDK) is introduced.
USB support is introduce for the SM8750 platform, and enabled in the MTP
and QRD devices.
On Hamoa, like on other devices the Asus Zenbook A14 definition of the
eDP panel is reworked to support both LCD and OLED configurations. WiFi
and Bluetooth is also enabled on the A14. The CRD gains support for
controlling charge limits.
The refgen regulator supplying DSI is defined and wired up on a variety
of platforms.
* tag 'qcom-arm64-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (138 commits)
arm64: dts: qcom: sdx75: Add missing usb-role-switch property
arm64: dts: qcom: sdx75: Flatten usb controller node
arm64: dts: qcom: HAMOA-IOT-SOM: Unreserve GPIOs blocking SPI11 access
arm64: dts: qcom: qrb2210-rb1: Fix UART3 wakeup IRQ storm
Revert "arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature"
arm64: dts: qcom: kodiak: add coresight nodes
arm64: dts: qcom: sdm845-oneplus: Describe TE gpio
arm64: dts: qcom: sdm845-oneplus: Implement panel sleep pinctrl
arm64: dts: qcom: sdm845-oneplus: Group panel pinctrl
arm64: dts: qcom: sdm845-oneplus: Update compatbible and add DDIC supplies
arm64: dts: qcom: qcs6490-rb3gen2: Rename vph-pwr regulator node
arm64: dts: qcom: qcm6490-fairphone-fp5: Add UW cam actuator
arm64: dts: qcom: qcm6490-fairphone-fp5: Enable CCI pull-up
arm64: dts: qcom: sm8750: Add USB support for SM8750 QRD platform
arm64: dts: qcom: sm8750: Add USB support for SM8750 MTP platform
arm64: dts: qcom: sm8750: Add USB support to SM8750 SoCs
arm64: dts: qcom: rename x1p42100 to purwa
arm64: dts: qcom: rename sc7280 to kodiak
arm64: dts: qcom: rename qcm2290 to agatti
arm64: dts: qcom: add gpu_zap_shader label
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.19-rc1
Document various new IPs on older chips, as well as some existing
developer kits that were missing compatible strings. Add power domain
IDs on Tegra264 and wake-up support for the XUSB controller on Tegra234.
* tag 'tegra-for-6.19-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: usb: Add wake-up support for Tegra234 XUSB host controller
dt-bindings: devfreq: tegra30-actmon: Add Tegra124 fallback for Tegra210
dt-bindings: display: tegra: Document Tegra20 and Tegra30 CSI
dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+
dt-bindings: arm: tegra: Document Jetson Nano Devkits
dt-bindings: power: Add power domain IDs for Tegra264
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.19 (take two)
- Add Imagination Technologies PowerVR Series 7XE GE7800 GPU support
for the R-Car M3-N and V3U SoCs,
- Add Ethernet support for the RZ/T2H and RZ/N2H SoCs and their
evaluation boards,
- Add ADC support for the RZ/N1D SoC,
- Add thermal, NMI pushbutton, and RTC support for the RZ/V2H SoC and
the RZ/V2H EVK development board,
- Add USB2.0 support for the RZ/G3S SoC and the RZ/G3S SMARC Carrier
II board.
* tag 'renesas-dts-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC
arm64: dts: renesas: r9a09g057: Add RTC node
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add NMI pushbutton support
arm64: dts: renesas: rzg3s-smarc: Enable USB support
arm64: dts: renesas: r9a08g045: Add USB support
arm64: dts: renesas: r9a09g057: Add TSU nodes
ARM: dts: renesas: r9a06g032: Add the ADC device
arm64: dts: renesas: r9a09g087: Add GMAC nodes
arm64: dts: renesas: r9a09g077: Add GMAC nodes
arm64: dts: renesas: r9a09g087: Add ETHSS node
arm64: dts: renesas: r9a09g077: Add ETHSS node
arm64: dts: renesas: r8a779a0: Add GE7800 GPU node
arm64: dts: renesas: r8a77965: Add GE7800 GPU node
dt-bindings: clock: r8a779a0: Add ZG core clock
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add clock and reset identifiers for the Video Input Interface.
These identifiers support two instances: VIIF0 and VIIF1.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Remove the definitions of number of clocks from bindings because they
prevent adding new clocks. Since the previous patch removed all refereces
within the driver, they can now be deleted.
The same for resets and plls.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add clock and reset ID defines for rv1126b.
Also add documentation for the rv1126b CRU core.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251111025738.869847-3-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add interconnect dt-bindings and driver support for Qualcomm Kaanapali SoC.
* icc-kaanapali
dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Kaanapali SoC
interconnect: qcom: add Kaanapali interconnect provider driver
dt-bindings: interconnect: qcom-bwmon: Document Kaanapali BWMONs
Link: https://lore.kernel.org/r/20251031-knp-interconnect-v4-0-568bba2cb3e5@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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The router link clock branches also feature some reset logic, which is
required to properly power sequence the hardware for DP tunneling over
USB4.
Describe these missing resets.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-topic-usb4_x1e_dispcc-v1-1-14c68d842c71@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add compatible string for SM8750 video clock controller and the bindings
for SM8750 Qualcomm SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-4-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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TH1520 SoC is divided into several subsystems, most of them have
distinct reset controllers. Let's document reset controllers other than
the one for VO subsystem and IDs for their reset signals.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP
reset controller, not the VO one which is documented as
"thead,th1520-reset" and is the only reset controller supported for
TH1520 for now.
Let's remove the IDs, leaving them to be implemented by AP-subsystem
reset controller in the future.
Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Add device tree binding documentation and header file for the ESWIN
eic7700 reset controller module.
Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Add definition for display subsystem reset control, so display
driver can reset display controller properly, clearing any
configuration left there by bootloader. Since 6.17 after
PM domains rework it became necessary for display to function.
Fixes: 0e789b491ba0 ("pmdomain: core: Leave powered-on genpds on until sync_state")
Cc: stable@vger.kernel.org # 6.17
Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20251116-sdm660-mdss-reset-v2-1-6219bec0a97f@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support for the AST2700 SoC in the ASPEED watchdog device tree
bindings. This includes:
- Adding "aspeed,ast2700-wdt" to the compatible string list.
- Extending the "aspeed,reset-mask" property description for AST2700.
- Defining AST2700-specific reset mask bits in aspeed-wdt.h,
covering RESET1 to RESET5.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
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Add defines for the pixel clock sampling modes (rising edge, falling edge,
dual edge) for parallel video interfaces.
This avoids hardcoded constants in device tree sources.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
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Introduce reset capability to EN7523 device-tree clock binding
documentation.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull more Samsung clk driver updates from Krzysztof Kozlowski:
- ExynosAutov920: add support for additional clock controllers (M2M and
MFC)
* tag 'samsung-clk-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: clk-pll: simplify samsung_pll_lock_wait()
clk: samsung: exynosautov920: add block mfc clock support
clk: samsung: exynosautov920: add clock support
dt-bindings: clock: exynosautov920: add mfc clock definitions
dt-bindings: clock: exynosautov920: add m2m clock definitions
dt-bindings: clock: google,gs101-clock: add power-domains
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Renesas RZ/V2N and RZ/V2H USB3.0 Core Clock DT Binding Definitions
USB3.0 core clock DT binding definitions for the Renesas RZ/V2N
(R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared by driver and DT source
files.
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Add definitions for USB3.0 core clocks in the R9A09G056 CPG DT bindings
header file.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251101050034.738807-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
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Add definitions for USB3.0 core clocks in the R9A09G057 CPG DT bindings
header file.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251101050034.738807-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
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Add documentation for i.MX8ULP's SIM LPAV module.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Link: https://lore.kernel.org/r/20251104120301.913-3-laurentiumihalcea111@gmail.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Renesas R-Car V3U Graphics Clock DT Binding Definition
Graphics Clock DT binding definition for the Renesas R-Car V3U
(R8A779A0) SoC, shared by driver and DT source files.
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Add the core clock used by the GPU on the Renesas R-Car V3U
(R8A779A0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251106211604.2766465-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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CLK_NR_CLKS has always only be used on the driver side to calculate array
sizes should never have been part of the clock-binding.
Let's drop it, since the kernel code no longer uses it either and nothing
else has ever used it.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20251103234032.413563-3-heiko@sntech.de
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The Trusted Firmware on RK3568 exposes 3 clocks via the SCMI clock
interface. Add descriptive IDs for them.
The clock ids are used in both the older vendor-binary TF-A, as well
as the recently merged upstream SCMI clock implementation.
Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/31265
Reviewed-by: Diederik de Haas <diederik@cknow-tech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251103234926.416137-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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into clk-for-6.19
Merge Kaanapali RPMh, TCSR and global clock controllers through a topic
branch, so they can be made available in the DeviceTree branch as well.
|
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Add device tree bindings for the global clock controller on Qualcomm
Kaanapali platform.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251030-gcc_kaanapali-v2-v2-3-a774a587af6f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add unique ID for Qualcomm QCS6490 SoC.
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251103-qcs6490_soc_id-v1-1-c139dd1e32c8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Kaanapali SoC
Document the RPMh Network-On-Chip Interconnect of the Kaanapali platform.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251031-knp-interconnect-v4-1-568bba2cb3e5@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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As like other SDX targets, SDX75 QPIC BCM resource is also modeled as a
RPMh clock in clk-rpmh driver. However, for SDX75, this resource was also
described as an interconnect node mistakenly.
Hence, drop the QPIC interconnect IDs and let the clients use clk-rpmh
driver to vote for this resource.
Even though this change is an ABI break, it is necessary to avoid
describing the same resource provider in two different drivers, as it may
lead to votes from clients overriding each other.
Fixes: 956329ec7c5e ("dt-bindings: interconnect: Add compatibles for SDX75")
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
[mani: kept the QUP defines value unchanged]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-2-20d6820e455c@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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into HEAD
Merge IPQ5424 DeviceTree bindings for the Network Subsystem clock
controller from topic branch, to gain access to binding constants.
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Add the ID for the Qualcomm SM8850 SoC which represents the Kaanapali
platform.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251022-knp-socid-v2-1-d147eadd09ee@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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|
There are three iommu in total, namely MM_IOMMU, APU_IOMMU, INFRA_IOMMU,
Add bindings for them.
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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into clk-for-6.19
Merge binding changes for IPQ5424 network subsystem clock controllers
through topic branch, to make them available for DeviceTree branch as
well.
|
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NSS clock controller provides the clocks and resets to the networking
blocks such as PPE (Packet Process Engine) and UNIPHY (PCS) on IPQ5424
devices.
Add support for the compatible string "qcom,ipq5424-nsscc" based on the
existing IPQ9574 NSS clock controller Device Tree binding. Additionally,
update the clock names for PPE and NSS for newer SoC additions like
IPQ5424 to use generic and reusable identifiers "nss" and "ppe" without
the clock rate suffix.
Also add master/slave ids for IPQ5424 networking interfaces, which is
used by nss-ipq5424 driver for providing interconnect services using
icc-clk framework.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-7-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
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The GCC clock GPLL0_OUT_AUX is one of source clocks for IPQ5424 NSS clock
controller.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-5-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
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Add the NSSNOC master/slave ids for Qualcomm IPQ5424 network subsystem
(NSS) hardware blocks. These will be used by the gcc-ipq5424 driver
that provides the interconnect services by using the icc-clk framework.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Acked-by: Georgi Djakov <djakov@kernel.org>
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-3-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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into clk-for-6.19
Merge the DeviceTree binding update adding the MDSS rese constant for
SM7150 through a topic branch to make available in DeviceTree branch as
well.
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Add the index for a reset inside the dispcc on SM7150 SoC.
Signed-off-by: Jens Reidel <adrian@mainlining.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250919-sm7150-dispcc-fixes-v1-1-308ad47c5fce@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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into arm64-for-6.19
Merge the topic branch adding MDSS reset constants for SM6350, so they
can be referenced from the MDSS node.
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into clk-for-6.19
Merge the DeviceTree binding update adding MDSS reset constants through
a topic branch to make available in DeviceTree branch as well.
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Add the indexes for two resets inside the dispcc on SM6350 SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250919-sm6350-mdss-reset-v1-1-48dcac917c73@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add power domain IDs for RV1126B SoC.
Add a new compatible because register fields have changed.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add support for the power controllers found in the MediaTek MT8196
Chromebook SoC.
This chip has three power controllers, two of which located in the
SCP subsystems (where one can be directly controlled and the other
can be controlled only through the HW Voter IP), and one located
in the Multimedia HFRP subsystem, controllable only through the HW
Voter IP.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add constants for voltage levels: LOW_SVS_D2_1, LOW_SVS_D1_1 and
LOW_SVS_L0.
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The firmware exposes clocks that can be controlled via the
Alive Clock and Power Manager (ACPM) interface.
Make the ACPM node a clock provider by adding the mandatory
"#clock-cells" property, which allows devices to reference its
clock outputs.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-1-321ee8826fd4@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Some of the USB4 muxes, RCGs and resets were not initially described.
Add indices for them to allow extending the driver.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the set of power domain IDs available on the Tegra264 SoC so that
they can be used in device tree files.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Driver is not used anymore. Remove header file.
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
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Add definitions for USB2 PHY core clocks in the R9A09G047 CPG DT
bindings header file.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251001212709.579080-9-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add device tree clock binding definitions for CMU_MFC
Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add device tree clock binding definitions for CMU_M2M
Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There's a bunch of patches here across drivers/clk/ to migrate drivers
to use struct clk_ops::determine_rate() instead of the round_rate()
one so that we can remove the round_rate clk_op entirely. Brian has
taken up that task which nobody else has wanted to do for close to a
decade. Thanks Brian!
This is all prerequisite work to get to the real task of improving the
clk rate setting process. Once we have determine_rate() used
everywhere, we'll be able to do things like chain the rate request
structs in linked lists to order the rate setting operations or add
more parameters without having to change every clk driver in
existence. It's also nice to not have multiple ways to do something
which just causes confusion for clk driver authors. Overall I'm glad
this is getting done.
Beyond this change we also have a tweak to the clk_lookup() function
in the core framework to use hashing on the clk name instead of a clk
tree walk with string comparisons. We _still_ rely on the clk name to
be unique, because historically we've used globally unique strings to
describe the clk tree topology. This tree walk becomes increasingly
slow as more clks are added to the system. Searching from the roots
for a duplicate is simple but pretty dumb and it wastes boot time so
we're using a hash table as an improvement. Ideally we wouldn't rely
on the strings to be unique at all, relegating them to simply debug
information, but that is future work that will likely require some
sort of Kconfig knob indicating strings aren't used for topology
description.
Outside of the core framework changes we have the usual new SoC
support and fixes to clk drivers for things that were discovered once
the clks were used by consumer drivers. Nothing in particular is
jumping out at me in the "misc" pile, except maybe the Amlogic driver
that has gone through a refactoring. That series got a fix from
testing in -next though so it seems likely that things have been
getting good test coverage for a couple weeks already"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits)
clk: microchip: core: remove duplicate roclk_determine_rate()
reset: aspeed: register AST2700 reset auxiliary bus device
dt-bindings: clock: ast2700: modify soc0/1 clock define
clk: tegra: do not overallocate memory for bpmp clocks
clk: ep93xx: Use int type to store negative error codes
clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
clk: loongson2: Avoid hardcoding firmware name of the reference clock
clk: loongson2: Allow zero divisors for dividers
clk: loongson2: Support scale clocks with an alternative mode
clk: loongson2: Allow specifying clock flags for gate clock
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
clk: clocking-wizard: Fix output clock register offset for Versal platforms
clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()
clk: mmp: pxa1908: Instantiate power driver through auxiliary bus
clk: s2mps11: add support for S2MPG10 PMIC clock
dt-bindings: clock: samsung,s2mps11: add s2mpg10
dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
clk: stm32: introduce clocks for STM32MP21 platform
dt-bindings: stm32: add STM32MP21 clocks and reset bindings
...
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* clk-aspeed:
reset: aspeed: register AST2700 reset auxiliary bus device
dt-bindings: clock: ast2700: modify soc0/1 clock define
* clk-rockchip:
clk: rockchip: rk3368: use clock ids for SCLK_MIPIDSI_24M
dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
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'clk-loongson' into clk-next
- Add Mediatek MT8196 clk drivers
* clk-marvell:
clk: mmp: pxa1908: Instantiate power driver through auxiliary bus
* clk-xilinx:
clk: clocking-wizard: Fix output clock register offset for Versal platforms
clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()
* clk-mediatek: (31 commits)
clk: mediatek: Add MT8196 vencsys clock support
clk: mediatek: Add MT8196 vdecsys clock support
clk: mediatek: Add MT8196 ovl1 clock support
clk: mediatek: Add MT8196 ovl0 clock support
clk: mediatek: Add MT8196 disp-ao clock support
clk: mediatek: Add MT8196 disp1 clock support
clk: mediatek: Add MT8196 disp0 clock support
clk: mediatek: Add MT8196 mfg clock support
clk: mediatek: Add MT8196 mdpsys clock support
clk: mediatek: Add MT8196 mcu clock support
clk: mediatek: Add MT8196 I2C clock support
clk: mediatek: Add MT8196 pextpsys clock support
clk: mediatek: Add MT8196 ufssys clock support
clk: mediatek: Add MT8196 peripheral clock support
clk: mediatek: Add MT8196 vlpckgen clock support
clk: mediatek: Add MT8196 topckgen2 clock support
clk: mediatek: Add MT8196 topckgen clock support
clk: mediatek: Add MT8196 apmixedsys clock support
dt-bindings: clock: mediatek: Describe MT8196 clock controllers
clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
...
* clk-loongson:
clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
clk: loongson2: Avoid hardcoding firmware name of the reference clock
clk: loongson2: Allow zero divisors for dividers
clk: loongson2: Support scale clocks with an alternative mode
clk: loongson2: Allow specifying clock flags for gate clock
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
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- Speed up clk_core_lookup() by using a hashtable
* clk-microchip:
ARM: at91: remove default values for PMC_PLL_ACR
clk: at91: add ACR in all PLL settings
clk: at91: sam9x7: Add peripheral clock id for pmecc
clk: at91: clk-master: Add check for divide by 3
clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
ARM: at91: pm: save and restore ACR during PLL disable/enable
* clk-lookup:
clk: Use hashtable for global clk lookups
clk: Sort include statements
* clk-st:
dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
clk: stm32: introduce clocks for STM32MP21 platform
dt-bindings: stm32: add STM32MP21 clocks and reset bindings
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* clk-scmi:
clk: scmi: Add duty cycle ops only when duty cycle is supported
* clk-qcom: (27 commits)
clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment
clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk
clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc'
clk: qcom: gcc: Add support for Global Clock controller found on MSM8937
dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller
clk: qcom: Select the intended config in QCS_DISPCC_615
clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register()
clk: qcom: alpha-pll: convert from round_rate() to determine_rate()
clk: qcom: milos: Constify 'struct qcom_cc_desc'
clk: qcom: gcc: Add support for Global Clock Controller
dt-bindings: clock: qcom: document the Glymur Global Clock Controller
clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL
clk: qcom: rpmh: Add support for Glymur rpmh clocks
clk: qcom: Add TCSR clock driver for Glymur SoC
dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller
dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs
clk: qcom: dispcc-glymur: Add support for Display Clock Controller
dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC
clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks
dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs
...
* clk-broadcom:
clk: bcm: rpi: Maximize V3D clock
clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing
clk: bcm: rpi: Add missing logs if firmware fails
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* clk-imx:
clk: imx95-blk-ctl: Save/restore registers when RPM routines are called
clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure
* clk-allwinner:
clk: sunxi-ng: add support for the A523/T527 MCU CCU
clk: sunxi-ng: div: support power-of-two dividers
clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock
dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock
clk: sunxi-ng: sun6i-rtc: Add A523 specifics
* clk-ti:
clk: keystone: sci-clk: use devm_kmemdup_array()
clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled
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* clk-samsung:
clk: s2mps11: add support for S2MPG10 PMIC clock
dt-bindings: clock: samsung,s2mps11: add s2mpg10
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
* clk-tegra:
clk: tegra: dfll: Add CVB tables for Tegra114
clk: tegra: Add DFLL DVCO reset control for Tegra114
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
* clk-amlogic:
clk: amlogic: fix recent code refactoring
clk: amlogic: c3-peripherals: use helper for basic composite clocks
clk: amlogic: align s4 and c3 pwm clock descriptions
clk: amlogic: add composite clock helpers
clk: amlogic: use the common pclk definition
clk: amlogic: introduce a common pclk definition
clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
clk: amlogic: move PCLK definition to clkc-utils
clk: amlogic: aoclk: use clkc-utils syscon probe
clk: amlogic: use probe helper in mmio based controllers
clk: amlogic: add probe helper for mmio based controllers
clk: amlogic: drop meson-clkcee
clk: amlogic: naming consistency alignment
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'clk-spacemit' into clk-next
* clk-bindings:
dt-bindings: clock: mediatek: Add power-domains property
dt-bindings: clock: silabs,si5341: Add missing properties
dt-bindings: clock: adi,axi-clkgen: add clock-output-names property
dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding
dt-bindings: clock: Convert silabs,si570 to DT schema
dt-bindings: clock: Convert silabs,si5341 to DT schema
dt-bindings: clock: Convert silabs,si514/544 to DT schema
* clk-cleanup:
clk: tegra: do not overallocate memory for bpmp clocks
clk: ep93xx: Use int type to store negative error codes
dt-bindings: clock: st: flexgen: remove deprecated compatibles
clk: st: flexgen: remove unused compatible
clk: clk-axi-clkgen: remove unneeded semicolon
clk: tegra: Remove redundant semicolons
clk: npcm: select CONFIG_AUXILIARY_BUS
clk: remove unneeded 'fast_io' parameter in regmap_config
* clk-renesas: (27 commits)
clk: renesas: r9a09g05[67]: Reduce differences
clk: renesas: r9a09g047: Add USB3.0 clocks/resets
clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
clk: renesas: r9a09g056: Add clock and reset entries for I3C
clk: renesas: r9a09g057: Add clock and reset entries for I3C
dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks
clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()
clk: renesas: rzv2h: Re-assert reset on deassert timeout
clk: renesas: rzg2l: Re-assert reset on deassert timeout
clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()
dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs
clk: renesas: r9a09g047: Add GPT clocks and resets
clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()
clk: renesas: rzg2l: convert from round_rate() to determine_rate()
clk: renesas: r9a07g04[34]: Use tabs instead of spaces
clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL
clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
clk: renesas: r9a08g045: Add MSTOP for GPIO
...
* clk-thead:
clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
clk: thead: support changing DPU pixel clock rate
clk: thead: add support for enabling/disabling PLLs
clk: thead: Correct parent for DPU pixel clocks
clk: thead: th1520-ap: fix parent of padctrl0 clock
clk: thead: th1520-ap: describe gate clocks with clk_gate
* clk-spacemit:
clk: spacemit: fix i2s clock
clk: spacemit: introduce pre-div for ddn clock
dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock
clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
clk: spacemit: fix sspax_clk
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull Char/Misc/IIO/Binder updates from Greg KH:
"Here is the big set of char/misc/iio and other driver subsystem
changes for 6.18-rc1.
Loads of different stuff in here, it was a busy development cycle in
lots of different subsystems, with over 27k new lines added to the
tree.
Included in here are:
- IIO updates including new drivers, reworking of existing apis, and
other goodness in the sensor subsystems
- MEI driver updates and additions
- NVMEM driver updates
- slimbus removal for an unused driver and some other minor updates
- coresight driver updates and additions
- MHI driver updates
- comedi driver updates and fixes
- extcon driver updates
- interconnect driver additions
- eeprom driver updates and fixes
- minor UIO driver updates
- tiny W1 driver updates
But the majority of new code is in the rust bindings and additions,
which includes:
- misc driver rust binding updates for read/write support, we can now
write "normal" misc drivers in rust fully, and the sample driver
shows how this can be done.
- Initial framework for USB driver rust bindings, which are disabled
for now in the build, due to limited support, but coming in through
this tree due to dependencies on other rust binding changes that
were in here. I'll be enabling these back on in the build in the
usb.git tree after -rc1 is out so that developers can continue to
work on these in linux-next over the next development cycle.
- Android Binder driver implemented in Rust.
This is the big one, and was driving a huge majority of the rust
binding work over the past years. Right now there are two binder
drivers in the kernel, selected only at build time as to which one
to use as binder wants to be included in the system at boot time.
The binder C maintainers all agreed on this, as eventually, they
want the C code to be removed from the tree, but it will take a few
releases to get there while both are maintained to ensure that the
rust implementation is fully stable and compliant with the existing
userspace apis.
All of these have been in linux-next for a while"
* tag 'char-misc-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (320 commits)
rust: usb: keep usb::Device private for now
rust: usb: don't retain device context for the interface parent
USB: disable rust bindings from the build for now
samples: rust: add a USB driver sample
rust: usb: add basic USB abstractions
coresight: Add label sysfs node support
dt-bindings: arm: Add label in the coresight components
coresight: tnoc: add new AMBA ID to support Trace Noc V2
coresight: Fix incorrect handling for return value of devm_kzalloc
coresight: tpda: fix the logic to setup the element size
coresight: trbe: Return NULL pointer for allocation failures
coresight: Refactor runtime PM
coresight: Make clock sequence consistent
coresight: Refactor driver data allocation
coresight: Consolidate clock enabling
coresight: Avoid enable programming clock duplicately
coresight: Appropriately disable trace bus clocks
coresight: Appropriately disable programming clocks
coresight: etm4x: Support atclk
coresight: catu: Support atclk
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC build fix from Arnd Bergmann:
"One commit for the dt bindings was missing from the dt branch, this
one is already pending in the clk tree that contains the corresponding
device driver"
* tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
dt-bindings: clock: Add ARTPEC-8 clock controller
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git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
Pull networking updates from Paolo Abeni:
"Core & protocols:
- Improve drop account scalability on NUMA hosts for RAW and UDP
sockets and the backlog, almost doubling the Pps capacity under DoS
- Optimize the UDP RX performance under stress, reducing contention,
revisiting the binary layout of the involved data structs and
implementing NUMA-aware locking. This improves UDP RX performance
by an additional 50%, even more under extreme conditions
- Add support for PSP encryption of TCP connections; this mechanism
has some similarities with IPsec and TLS, but offers superior HW
offloads capabilities
- Ongoing work to support Accurate ECN for TCP. AccECN allows more
than one congestion notification signal per RTT and is a building
block for Low Latency, Low Loss, and Scalable Throughput (L4S)
- Reorganize the TCP socket binary layout for data locality, reducing
the number of touched cachelines in the fastpath
- Refactor skb deferral free to better scale on large multi-NUMA
hosts, this improves TCP and UDP RX performances significantly on
such HW
- Increase the default socket memory buffer limits from 256K to 4M to
better fit modern link speeds
- Improve handling of setups with a large number of nexthop, making
dump operating scaling linearly and avoiding unneeded
synchronize_rcu() on delete
- Improve bridge handling of VLAN FDB, storing a single entry per
bridge instead of one entry per port; this makes the dump order of
magnitude faster on large switches
- Restore IP ID correctly for encapsulated packets at GSO
segmentation time, allowing GRO to merge packets in more scenarios
- Improve netfilter matching performance on large sets
- Improve MPTCP receive path performance by leveraging recently
introduced core infrastructure (skb deferral free) and adopting
recent TCP autotuning changes
- Allow bridges to redirect to a backup port when the bridge port is
administratively down
- Introduce MPTCP 'laminar' endpoint that con be used only once per
connection and simplify common MPTCP setups
- Add RCU safety to dst->dev, closing a lot of possible races
- A significant crypto library API for SCTP, MPTCP and IPv6 SR,
reducing code duplication
- Supports pulling data from an skb frag into the linear area of an
XDP buffer
Things we sprinkled into general kernel code:
- Generate netlink documentation from YAML using an integrated YAML
parser
Driver API:
- Support using IPv6 Flow Label in Rx hash computation and RSS queue
selection
- Introduce API for fetching the DMA device for a given queue,
allowing TCP zerocopy RX on more H/W setups
- Make XDP helpers compatible with unreadable memory, allowing more
easily building DevMem-enabled drivers with a unified XDP/skbs
datapath
- Add a new dedicated ethtool callback enabling drivers to provide
the number of RX rings directly, improving efficiency and clarity
in RX ring queries and RSS configuration
- Introduce a burst period for the health reporter, allowing better
handling of multiple errors due to the same root cause
- Support for DPLL phase offset exponential moving average,
controlling the average smoothing factor
Device drivers:
- Add a new Huawei driver for 3rd gen NIC (hinic3)
- Add a new SpacemiT driver for K1 ethernet MAC
- Add a generic abstraction for shared memory communication
devices (dibps)
- Ethernet high-speed NICs:
- nVidia/Mellanox:
- Use multiple per-queue doorbell, to avoid MMIO contention
issues
- support adjacent functions, allowing them to delegate their
SR-IOV VFs to sibling PFs
- support RSS for IPSec offload
- support exposing raw cycle counters in PTP and mlx5
- support for disabling host PFs.
- Intel (100G, ice, idpf):
- ice: support for SRIOV VFs over an Active-Active link
aggregate
- ice: support for firmware logging via debugfs
- ice: support for Earliest TxTime First (ETF) hardware offload
- idpf: support basic XDP functionalities and XSk
- Broadcom (bnxt):
- support Hyper-V VF ID
- dynamic SRIOV resource allocations for RoCE
- Meta (fbnic):
- support queue API, zero-copy Rx and Tx
- support basic XDP functionalities
- devlink health support for FW crashes and OTP mem corruptions
- expand hardware stats coverage to FEC, PHY, and Pause
- Wangxun:
- support ethtool coalesce options
- support for multiple RSS contexts
- Ethernet virtual:
- Macsec:
- replace custom netlink attribute checks with policy-level
checks
- Bonding:
- support aggregator selection based on port priority
- Microsoft vNIC:
- use page pool fragments for RX buffers instead of full pages
to improve memory efficiency
- Ethernet NICs consumer, and embedded:
- Qualcomm: support Ethernet function for IPQ9574 SoC
- Airoha: implement wlan offloading via NPU
- Freescale
- enetc: add NETC timer PTP driver and add PTP support
- fec: enable the Jumbo frame support for i.MX8QM
- Renesas (R-Car S4):
- support HW offloading for layer 2 switching
- support for RZ/{T2H, N2H} SoCs
- Cadence (macb): support TAPRIO traffic scheduling
- TI:
- support for Gigabit ICSS ethernet SoC (icssm-prueth)
- Synopsys (stmmac): a lot of cleanups
- Ethernet PHYs:
- Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS
driver
- Support bcm63268 GPHY power control
- Support for Micrel lan8842 PHY and PTP
- Support for Aquantia AQR412 and AQR115
- CAN:
- a large CAN-XL preparation work
- reorganize raw_sock and uniqframe struct to minimize memory
usage
- rcar_canfd: update the CAN-FD handling
- WiFi:
- extended Neighbor Awareness Networking (NAN) support
- S1G channel representation cleanup
- improve S1G support
- WiFi drivers:
- Intel (iwlwifi):
- major refactor and cleanup
- Broadcom (brcm80211):
- support for AP isolation
- RealTek (rtw88/89) rtw88/89:
- preparation work for RTL8922DE support
- MediaTek (mt76):
- HW restart improvements
- MLO support
- Qualcomm/Atheros (ath10k):
- GTK rekey fixes
- Bluetooth drivers:
- btusb: support for several new IDs for MT7925
- btintel: support for BlazarIW core
- btintel_pcie: support for _suspend() / _resume()
- btintel_pcie: support for Scorpious, Panther Lake-H484 IDs"
* tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1536 commits)
net: stmmac: Add support for Allwinner A523 GMAC200
dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible
Revert "Documentation: net: add flow control guide and document ethtool API"
octeontx2-pf: fix bitmap leak
octeontx2-vf: fix bitmap leak
net/mlx5e: Use extack in set rxfh callback
net/mlx5e: Introduce mlx5e_rss_params for RSS configuration
net/mlx5e: Introduce mlx5e_rss_init_params
net/mlx5e: Remove unused mdev param from RSS indir init
net/mlx5: Improve QoS error messages with actual depth values
net/mlx5e: Prevent entering switchdev mode with inconsistent netns
net/mlx5: HWS, Generalize complex matchers
net/mlx5: Improve write-combining test reliability for ARM64 Grace CPUs
selftests/net: add tcp_port_share to .gitignore
Revert "net/mlx5e: Update and set Xon/Xoff upon MTU set"
net: add NUMA awareness to skb_attempt_defer_free()
net: use llist for sd->defer_list
net: make softnet_data.defer_count an atomic
selftests: drv-net: psp: add tests for destroying devices
selftests: drv-net: psp: add test for auto-adjusting TCP MSS
...
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git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- Added a new V4L2 clock helper
- New camera sensor drivers
- iris: Enable H.264/H.265 encoder support and fixes in iris driver
common code
- camss: add support for new SoC flavors
- venus: add new SoC support
- tc358743: support more infoframe types
- Various fixes, driver improvements and cleanups
* tag 'media/v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (439 commits)
media: venus: pm_helpers: add fallback for the opp-table
media: qcom: camss: vfe: Fix BPL alignment for QCM2290
media: tuner: xc5000: Fix use-after-free in xc5000_release
media: i2c: tc358743: Fix use-after-free bugs caused by orphan timer in probe
media: b2c2: Fix use-after-free causing by irq_check_work in flexcop_pci_remove
media: vsp1: Export missing vsp1_isp_free_buffer symbol
media: renesas: vsp1: Convert to SYSTEM_SLEEP/RUNTIME_PM_OPS()
media: renesas: ceu: Convert to RUNTIME_PM_OPS()
media: renesas: fdp1: Convert to RUNTIME_PM_OPS()
media: renesas: rcar-vin: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
media: renesas: rcar_drif: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
media: uvcvideo: Mark invalid entities with id UVC_INVALID_ENTITY_ID
media: uvcvideo: Support UVC_CROSXU_CONTROL_IQ_PROFILE
media: uvcvideo: Run uvc_ctrl_init_ctrl for all controls
media: uvcvideo: Shorten the transfer size non compliance message
media: uvcvideo: Do not re-reference dev->udev
media: uvcvideo: Use intf instead of udev for printks
media: uvcvideo: Move video_device under video_queue
media: uvcvideo: Drop stream->mutex
media: uvcvideo: Move MSXU_CONTROL_METADATA definition to header
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
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Pull SoC dt updates from Arnd Bergmann:
"There are five sets of new SoCs that get added in existing families,
all of them being either upgrades or cut-down versions of the older
chips:
- Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
of high-end workstations and laptops from Apple. Linux has been
working on these for a while but stil requires patches.
- Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
unlike the earlier Armv7 Artpec6 from the same company that was
part of a separate family of chips.
- NXP i.MX91 is a cut-down version of i.MX93, using only a single
Cortex-A55 core.
- Qualcomm Lemans Auto is a variant of the Lemans SoC that was
originally merged under the sa8775p name, the differences being
mostly the firmware configuration of the platform.
- Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
bedded SoCs based on Cortex-A55 cores
In total, there are 65 new machines, including:
- Industrial embedded system and single-board computers based on NXP,
Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
- Reference boards for the newly added Renesas, Qualcomm, NXP and
Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC
- Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
chips.
- Several Samsung phones using Qualcomm Snapdragon chips
- Set-top boxes based on Allwinner H313
- Five BMC boards using 32-bit ASpeed SoCs
- Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
(ARMv7) SoCs
Two machines get phased out because they were available only in small
quantities but never made it into products: one STi407 based reference
board, and a Snapdragon 845 based Chromebook.
Aside from the newly added machines, a lot of work went into improving
hardware support on the existing machines and cleaning up contents for
validation"
* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
ARM: dts: microchip: sam9x7: Add qspi controller
arm64: dts: qcom: Add MST pixel streams for displayport
arm64: dts: qcom: sm6350: correct DP compatibility strings
arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
arm64: dts: allwinner: h313: Add Amediatech X96Q
dt-bindings: arm: sunxi: Add Amediatech X96Q
arm64: dts: apple: t8015: Add SPMI node
arm64: dts: apple: t8012: Add SPMI node
arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
arm64: dts: rockchip: update pinctrl names for Radxa E52C
arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
arm64: dts: apple: Add J474s, J475c and J475d device trees
arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
...
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git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull thermal control updates from Rafael Wysocki:
"These are mostly thermal driver updates, including new thermal drivers
for Renesas RZ/G3S and Renesas RZ/G3E SoCs, a new power slider
platform feature support in the Intel int340x thermal driver, a new
Tegra114- specific SOCTHERM driver and more.
There is also a Step-wise thermal governor update allowing it to start
reducing cooling somewhat earlier if the temperature of the given
thermal zone is falling down and a thermal testing code cleanup.
Specifics:
- Add new thermal driver for the Renesas RZ/G3S SoC (Claudiu Beznea)
- Add new thermal driver for the Renesas RZ/G3E SoC (John Madieu)
- Add support for new platform power slider feature to the Intel
int340x driver (Srinivas Pandruvada).
- Add new Tegra114-specific SOCTHERM driver and document Tegra114
SOCTHERM Thermal Management System in DT bindings (Svyatoslav
Ryhel)
- Add temperature sensor channel to thermal-generic-adc (Svyatoslav
Ryhel)
- Add support for per-SoC default trim values to the Renesas
rcar_gen3 thermal driver, use it for adding R-Car V4H default trim
values, fix a comment typo in that driver and document Gen4 support
in its Kconfig entry (Marek Vasut)
- Fix mapping SoCs to generic Gen4 entry in the Renesas rcar_gen3
thermal driver (Wolfram Sang)
- Document the TSU unit in the r9a08g045-tsu and r9a09g047-tsu DT
bindings (Claudiu Beznea, John Madieu)
- Make LMH select QCOM_SCM and add missing IRQ includes to the
qcom/lmh thermal driver (Dmitry Baryshkov)
- Fix incorrect error message in the qcom/lmh thermal driver (Sumeet
Pawnikar)
- Add QCS615 compatible to tsens thermal DT bindings (Gaurav Kohli)
- Document the Glymur temperature sensor in qcom-tsens thermal DT
bindings (Manaf Meethalavalappu Pallikunhi)
- Make k3_j72xx_bandgap thermal driver register the thermal sensor
with hwmon (Michael Walle)
- Tighten GRF requirements in the rockchip thermal DT bindings,
silence a GRF warning in the rockchip thermal driver and unify
struct rockchip_tsadc_chip format in it (Sebastian Reichel)
- Update the Step-wise thermal governor to allow it to reduce the
cooling level earlier if thermal zone temperature is dropping and
clean it up (Rafael Wysocki)
- Clean up the thermal testing code (Rafael Wysocki)
- Assorted cleanups of thermal drivers (Jiapeng Chong, Salah Triki,
Osama Abdelkader)"
* tag 'thermal-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (37 commits)
thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas RZ/G3E SoC
dt-bindings: thermal: qcom-tsens: Document the Glymur temperature Sensor
thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas RZ/G3E SoC
dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
thermal/drivers/thermal-generic-adc: Add temperature sensor channel
dt-bindings: thermal: rockchip: Tighten grf requirements
thermal/drivers/rockchip: Shut up GRF warning
thermal/drivers/rockchip: Unify struct rockchip_tsadc_chip format
thermal/drivers/renesas/rzg3s: Add thermal driver for the Renesas RZ/G3S SoC
dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit
thermal/drivers/k3_j72xx_bandgap: Register sensors with hwmon
thermal/drivers/rcar_gen3: Fix mapping SoCs to generic Gen4 entry
thermal/drivers/tegra: Add Tegra114 specific SOCTHERM driver
dt-bindings: thermal: add Tegra114 soctherm header
thermal/drivers/tegra/soctherm-fuse: Prepare calibration for Tegra114 support
dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System
thermal/drivers/rcar_gen3: Document Gen4 support in Kconfig entry
thermal/drivers/rcar_gen3: Fix comment typo
drivers/thermal/qcom/lmh: Fix incorrect error message
thermal/drivers/qcom/lmh: Add missing IRQ includes
...
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"We have GPIO awareness in the pin control core and an interesting
AAEON driver.
Core changes:
- Allow pins to be identified/marked as GPIO mode with a special
callback.
The pin controller core is now "aware" if a pin is in GPIO mode if
the callback is implemented in the driver, and can thus be marked
as "strict", i.e. disallowing simultaneous use of a line as GPIO
and another function such as I2C.
This is enabled in the Qualcomm TLMM driver and also implemeted
from day 1 in the new Broadcom STB driver
- Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL
to better describe what the config is doing, as well as making it
more intuitive what shall be returned when reading this property
New drivers:
- Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver
- Qualcomm Glymur family pin controller driver
- Broadcom STB family pin controller driver
- Tegra186 pin controller driver
- AAEON UP pin controller support.
This is some special pin controller that works as an external
advanced line MUX and amplifier for signals from an Intel SoC. A
cooperative effort with the GPIO maintainer was needed to reach a
solution where we reuse code from the GPIO aggregator/forwarder
driver
- Renesas RZ/T2H and RZ/N2H pin controller support
- Axis ARTPEC-8 subdriver for the Samsung pin controller driver
Improvements:
- Output enable (OEN) support in the Renesas RZG2L driver
- Properly support bias pull up/down in the pinctrl-single driver
- Move over all GPIO portions using generic MMIO GPIO to the new
generic GPIO chip management which has a nice and separate API
- Proper DT bindings for some older Broadcom SoCs
- External GPIO (EGPIO) support in the Qualcomm SM8250
Deleted code:
- Dropped the now unused Samsung S3C24xx drivers"
* tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
pinctrl: use more common syntax for compound literals
pinctrl: Simplify printks with pOF format
pinctrl: qcom: Add SDM660 LPASS LPI TLMM
dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets
pinctrl: qcom: Add glymur pinctrl driver
dt-bindings: pinctrl: qcom: Add Glymur pinctrl
pinctrl: qcom: sm8250: Add egpio support
pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL
pinctrl: keembay: fix double free in keembay_build_functions()
pinctrl: spacemit: fix typo in PRI_TDI pin name
pinctrl: eswin: Fix regulator error check and Kconfig dependency
pinctrl: bcm: Add STB family pin controller driver
dt-bindings: pinctrl: Add support for Broadcom STB pin controller
pinctrl: qcom: make the pinmuxing strict
pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions
pinctrl: qcom: add infrastructure for marking pin functions as GPIOs
pinctrl: allow to mark pin functions as requestable GPIOs
pinctrl: qcom: use generic pin function helpers
pinctrl: make struct pinfunction a pointer in struct function_desc
...
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git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
- amlogic: Add support for S6/S7/S7D power-domains controller
- imx: Add support for i.MX91 power-domains
- marvell: Add support for PXA1908 power-domains
- mediatek:
- Add support for modem power sequence
- Add support for RTFF Hardware in MT8196/MT6991
- qcom: Align power-domain definitions for rpmpd
- rockchip: Default to use power-domain support
- thead: Create auxiliary device along with a corresponding reset
driver
- ti: Synchronize on/off state with HW-state for ti-sci power-domains
* tag 'pmdomain-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (25 commits)
pmdomain: thead: Fix error pointer vs NULL bug in th1520_pd_reboot_init()
pmdomain: thead: create auxiliary device for rebooting
driver: reset: th1520-aon: add driver for poweroff/reboot via AON FW
pmdomain: mediatek: airoha: convert from round_rate() to determine_rate()
pmdomain: rockchip: enable ROCKCHIP_PM_DOMAINS with ARCH_ROCKCHIP
pmdomain: marvell: Add PXA1908 power domains
dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu
pmdomain: ti-sci: Set PD on/off state according to the HW state
pmdomain: amlogic: Add support for S6 S7 S7D power domains controller
dt-bindings: power: add Amlogic S6 S7 S7D power domains
pmdomain: mediatek: Convert all SoCs to new style regmap retrieval
pmdomain: mediatek: Add support for RTFF Hardware in MT8196/MT6991
pmdomain: mediatek: Add support for modem power sequences
pmdomain: mediatek: Move ctl sequences out of power_on/off functions
pmdomain: mediatek: Handle SoCs with inverted SRAM power-down bits
pmdomain: mediatek: Refactor bus protection regmaps retrieval
dt-bindings: power: mediatek: Document access-controllers property
pmdomain: remove unneeded 'fast_io' parameter in regmap_config
pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91
pmdomain: imx93-blk-ctrl: use ARRAY_SIZE() instead of hardcode number
...
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git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio updates from Bartosz Golaszewski:
"There are two new drivers and support for more models in existing
ones.
The generic GPIO API has been reworked and all users converted
which allowed us to move the fields specific to the generic GPIO
implementation out of the high-level struct gpio_chip into its own
structure that wraps the gpio_chip.
Other than that, there's nothing too exciting. Mostly minor tweaks and
fixes all over the place, some refactoring and some small new features
in helper modules.
GPIO core:
- add support for sparse pin ranges to the glue between GPIO and
pinctrl
- use a common prefix across all GPIO descriptor flags for improved
namespacing
New drivers:
- add new GPIO driver for the Nuvoton NCT6694
- add new GPIO driver for MAX7360
Driver improvements:
- add support for Tegra 256 to the gpio-tegra186 driver
- add support for Loongson-2K0300 to the gpio-loongson-64bit driver
- refactor the gpio-aggregator module to expose its GPIO forwarder
API to other in-kernel users (to enable merging of a new pinctrl
driver that uses it)
- convert all remaining drivers to using the modernized generic GPIO
chip API and remove the old interface
- stop displaying global GPIO numbers in debugfs output of controller
drivers
- extend the gpio-regmap helper with a new config option and improve
its support for GPIO interrupts
- remove redundant fast_io parameter from regmap configs in GPIO
drivers that already use MMIO regmaps which imply it
- add support for a new model in gpio-mmio: ixp4xx expansion bus
- order includes alphabetically in a few drivers for better
readability
- use generic device properties where applicable
- use devm_mutex_init() where applicable
- extend build coverage of drivers by enabling more to be compiled
with COMPILE_TEST enabled
- allow building gpio-stmpe as a module
- use dev_err_probe() where it makes sense in drivers
Late driver fixes:
- fix setting GPIO direction to output in gpio-mpfs
Documentation:
- document the usage of software nodes with GPIO chips
Device-tree bindings:
- Add DT bindings documents for new hardware: Tegra256, MAX7360
- Document a new model in Loongson bindings: LS2K0300
- Document a new model using the generic GPIO binding: IXP4xx
- Convert the DT binding for fsl,mxs-pinctrl to YAML
- fix the schema ID in the "trivial" GPIO schema
- describe GPIO hogs in the generic GPIO binding"
* tag 'gpio-updates-for-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (122 commits)
gpio: mpfs: fix setting gpio direction to output
gpio: generic: move GPIO_GENERIC_ flags to the correct header
gpio: generic: rename BGPIOF_ flags to GPIO_GENERIC_
gpio: nomadik: fix the debugfs helper stub
MAINTAINERS: Add entry on MAX7360 driver
input: misc: Add support for MAX7360 rotary
input: keyboard: Add support for MAX7360 keypad
gpio: max7360: Add MAX7360 gpio support
gpio: regmap: Allow to provide init_valid_mask callback
gpio: regmap: Allow to allocate regmap-irq device
pwm: max7360: Add MAX7360 PWM support
pinctrl: Add MAX7360 pinctrl driver
mfd: Add max7360 support
dt-bindings: mfd: gpio: Add MAX7360
rtc: Add Nuvoton NCT6694 RTC support
hwmon: Add Nuvoton NCT6694 HWMON support
watchdog: Add Nuvoton NCT6694 WDT support
can: Add Nuvoton NCT6694 CANFD support
i2c: Add Nuvoton NCT6694 I2C support
gpio: Add Nuvoton NCT6694 GPIO support
...
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This adds header for the Tegra114 SOCTHERM device tree node.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://lore.kernel.org/r/20250828055104.8073-5-clamor95@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
Memory controller drivers for v6.18
1. STM32 OMM: Fix ineffective/missing setting of the req2ack in the
device based on DT property, if the value is different than 0.
2. Samsung Exynos SROM: Fix IO map resource leak if
of_platform_populate() in probe() failed.
3. Broadcom brcmstb: Document existing, older devices in Devicetree
bindings.
4. Tegra 210 EMC: Document OPP table for interconnects (driver usage
will come later) and define memory client IDs as bindings, because
these are shared between DTS and driver.
* tag 'memory-controller-drv-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: tegra210: Use bindings for client ids
dt-bindings: memory: tegra210: Add memory client IDs
dt-bindings: memory: tegra210: emc: Document OPP table and interconnect
dt-bindings: memory: Update brcmstb-memc-ddr binding with older chips
memory: samsung: exynos-srom: Fix of_iomap leak in exynos_srom_probe
memory: stm32_omm: Fix req2ack update test
Link: https://lore.kernel.org/r/20250912140030.204650-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner Device Tree changes for 6.18
This tag contains two DT binding header changes that are shared with
the clk tree.
In this cycle we gained support for the MCU PRCM clock and reset
controller on the A523/A527/T527 family of SoCs, the NPU which is a
Vivante GC9000 IP block, and the NPU clock that was missing. The other
PRCM clock controller gained default bus clock rate settings. These
were not configured in the upstream U-boot bootloader, leading to them
running at slower rates. The assigned rates are from the user manual.
There is also a new board, the NetCube Systems Nagami SoM and two of
its carrier boards.
The A523 family development boards now have their internal RTC clocks
configured correctly, so that the RTC does not drift wildly. The missing
functions for the AXP717 on these boards are added. Missing reset GPIOs
and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its
LEDs described and usable.
An overlay for the Orange Pi Zero interface (addon) board was added.
This can be used with the Orange Pi Zero and Zero Plus 2. Default audio
routing for these two boards (to be used with the addon) were added to
complement the overlay.
* tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions
arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal
arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal
arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal
arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks
ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier
ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier
ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings
ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay
ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing
ARM: dts: allwinner: orangepi-zero: Add default audio routing
arm64: dts: allwinner: a523: Add NPU device node
arm64: dts: allwinner: a523: Add MCU PRCM CCU node
dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock
arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting
arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting
arm64: dts: allwinner: a527: cubie-a5e: Add LEDs
Link: https://lore.kernel.org/r/aMrtuZg8HlR--TAt@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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-add SOC0_CLK_AHBMUX:
add SOC0_CLK_AHBMUX for ahb clock source divide.
mpll->
ahb_mux -> div_table -> clk_ahb
hpll->
-new add clock:
SOC0_CLK_MPHYSRC: UFS MPHY clock source.
SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source.
SOC1_CLK_I3C: I3C clock source.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Document the clock controller shipped in Loongson-2K0300 SoC, which
generates various clock signals for SoC peripherals. Differing from
previous generations of SoCs, LS2K0300 requires a 120MHz external clock
input.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Adds clock and reset binding entries for STM32MP21 SoC family.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Introduce binding documentation for system clocks, functional clocks,
and PEXTP0/1 and UFS reset controllers on MediaTek MT8196.
This binding also includes a handle to the hardware voter, a
fixed-function MCU designed to aggregate votes from the application
processor and other remote processors to manage clocks and power
domains.
The HWV on MT8196/MT6991 is incomplete and requires software to manually
enable power supplies, parent clocks, and FENC, as well as write to both
the HWV MMIO and the controller registers.
Because of these constraints, the HWV cannot be modeled using generic
clock, power domain, or interconnect APIs. Instead, a custom phandle is
exceptionally used to provide direct, syscon-like register access to
drivers.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add the missing AFE Merge Interface clock to MT7622 to make use of
it in the audio subsystem.
While at it, also remove the useless CLK_AUDIO_NR_CLK definition.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Previously, the K1 clock driver did not include the parent clocks of
the I2S sysclk.
Introduce pre-clock to fix I2S clock.
Otherwise, the I2S clock may not work as expected.
This patch adds their definitions to allow proper registration
in the driver and usage in the device tree.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add required syscon compatible and #power-domain-cells to the APMU
controller. This is required for the SoC's power domain controller as
the registers are shared.
Device tree bindings for said power domains are also added.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add device tree binding support for RZ/T2H and RZ/N2H SoCs to the
existing RZ/N1 MIIC converter binding. These SoCs share similar MIIC
functionality but have architectural differences that require schema
updates.
Add new compatible strings "renesas,r9a09g077-miic" for RZ/T2H and
"renesas,r9a09g087-miic" for RZ/N2H, with the latter falling back to
the RZ/T2H variant. The new SoCs require reset support with two reset
lines for converter register reset and converter reset, which are not
present on RZ/N1.
Update port configurations to accommodate the different architectures.
RZ/N1 supports 5 ports numbered 1-5 with complex input mappings
covering indices 0-13, while RZ/T2H and RZ/N2H support 4 ports
numbered 0-3 with simplified input mappings covering indices 0-8.
Extend the switch port configuration property to support value 0 for
the new SoCs.
Add a new dt-bindings header file with media interface connection
matrix constants that map GMAC, ESC, and ETHSW ports to numeric
identifiers for use with RZ/T2H and RZ/N2H device trees.
Update DT schema validation to ensure proper port numbering and input
mappings per SoC variant.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250910204132.319975-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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into soc/drivers
This pull request contains Broadcom SoC drivers updates for 6.18:
- Andrea adds the missing MIPI DSI clock defines for the RP1 and then
continues to implement the remaining clocks for the RP1 chip (ADC,
I2S, Audio in/out, DMA, MIPI, PWM, SDIO, UART, encoder)
- Akhilesh fixes a spelling typo in the bcm47xx_sprom driver
- Brian converts the RP1 clock driver to use the new determine_rate()
API
* tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux:
clk: rp1: convert from round_rate() to determine_rate()
drivers: firmware: bcm47xx_sprom: fix spelling
clk: rp1: Implement remaining clock tree
dt-bindings: clock: rp1: Add missing MIPI DSI defines
Link: https://lore.kernel.org/r/20250910171910.666401-4-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.18-rc1
Support for the Tegra264 generation of I2C is documented as well as some
older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices.
Contained are also some additions to existing bindings for Tegra114 and
a fix for the power supply feeding VI/CSI.
* tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
Link: https://lore.kernel.org/r/20250914063927.89981-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.18
Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
Lemans EVK.
The SDM845 Cheza development boards are removed, as they are not longer
in use.
For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
buses are added and the internal GE PHY.
IPQ5424 gets CPU frequency scaling and a missing UART.
The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
name. The IoT memory map introduced and made the default, GDSP FastRPC
and GPR nodes are added.
Touch keys are enabled on the BQ Aquaris X5 Plus.
On QCM2290 the video accelerator is enabled, so is HS timing modes for
eMMC.
The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
PCIe controller is introduced.
On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
eMMC support and generic packer router (GPR).
On the Monaco Ride board, the eMMC controller is enabled.
On QRB220 RB1, the venus video accelerator is enabled.
For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
LPASS, and USB offload support is added, the codecs and sound card is
then described on the QCM6490 IDP. The MDSS core reset is introduced, to
clear bootloader configuration on SC7280-based devices.
On Fairphone5, USB audio offload is added.
AudioReach support on SC7280 (QCS6490) is introduced and used to
enable sound on the RB3Gen2 board.
The video clock controller is added to SC8180X.
On SC8280XP the GPI DMA controllers are described and enabled.
Display and GPU is enabled for the Fairphone 3 and charging is enabled
on the Google Pixel 3a.
The routing for the second USB connector on the Lenovo Yoga C630 is
described.
On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
encoder/decoder (venus).
On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
introduced and on Fairphone4 the USB audio offload support is enabled.
On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
functionality.
On SM8650 ACD levels are added for the GPU.
Camera and video clock controllers power-domains are updated on SM8450,
SM8550, and SM8650, now that support for multiple power-domains is
accepted.
SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.
The DWC3 glue and core nodes are flattened on a number of platforms.
USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
variety of platforms, now that the QMP PHY driver supports this.
Platform specific RPMh PD constants are replaced with generic constants
wherever possible.
On X Elite the PM8010 is disabled by default, removing boot splats
on a variety of boards without this PMIC, the video clock controller is
added.
For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
marked as valid for the external DisplayPorts. The fingerprint reader
found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.
GPU support is added for the X Plus SoC.
* tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits)
arm64: dts: qcom: x1e80100: Update GPU OPP table
arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC
arm64: dts: qcom: add initial support for Samsung Galaxy S20
dt-bindings: arm: qcom: document x1q board binding
arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi
arm64: dts: qcom: lemans-evk: Add sound card
arm64: dts: qcom: lemans: Add gpr node
arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel
arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec
arm64: dts: qcom: sm6150: add venus node to devicetree
arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT
arm64: dts: qcom: qrb2210-rb1: Enable Venus
arm64: dts: qcom: qcm2290: Add Venus video node
arm64: dts: qcom: monaco-evk: Add sound card
arm64: dts: qcom: qcs8300: Add gpr node
arm64: dts: qcom: qcs8300: Add Monaco EVK board
dt-bindings: arm: qcom: Add Monaco EVK support
arm64: dts: qcom: qcm6490-idp: Add sound card
arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
arm64: dts: qcom: qcs6490-rb3gen2: Add sound card
...
Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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There are four clock controllers in the A523 SoC. The existing binding
already covers two of them that are critical for basic operation. The
remaining ones are the MCU clock controller and CPU PLL clock
controller.
Add a description for the MCU CCU. This unit controls and provides
clocks to the MCU (RISC-V) subsystem and peripherals meant to operate
under low power conditions.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The main clock controller on the A523/T527 has the NPU's module clock.
It was missing from the original submission, likely because that was
based on the A523 user manual; the A523 is marketed without the NPU.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Renesas RZ/G3E USB3.0 Core Clock DT Binding Definitions
USB3.0 core clock DT binding definitions for the Renesas RZ/G3E
(R9A09G047) SoC, shared by driver and DT source files.
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Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
header file.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250909180803.140939-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The way that resets are handled on these Tegra devices is that there is a
set of peripheral clocks & resets which are paired up. This is because they
are laid out in banks within the CAR (clock and reset) controller. In most
cases we're referring to those resets, so you'll often see a clock ID used
in conjection with the same reset ID for a given IP block.
In addition to those peripheral resets, there are a number of extra resets
that don't have a corresponding clock and which are exposed in registers
outside of the peripheral banks, but still part of the CAR. To support
those "special" registers, the TEGRA*_RESET() is used to denote resets
outside of the regular peripheral resets. Essentially it defines the offset
within the CAR at which special resets start. In the above case, Tegra114
has 5 banks with 32 peripheral resets each. The first special reset,
TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0 = 160.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Each memory client has unique hardware ID, add these IDs.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Replace hverkuil@xs4all.nl by hverkuil@kernel.org.
Signed-off-by: Hans Verkuil <hverkuil@kernel.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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Add compatible strings for the four SCU interrupt controller instances
on the AST2700 SoC (scu-ic0 to 3), following the multi-instance model used
on AST2600.
Also define interrupt indices in the binding header.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/all/20250908011812.1033858-4-ryan_chen@aspeedtech.com
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Add clock management unit bindings for PERIC0 and PERIC1 blocks
which provide clocks for USI, I2C and UART peripherals.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add the missing LHS_ACEL clock ID for the HSI0 block. This clock is
required for proper USB operation, as without it, USB connections fail
with errors like device descriptor read timeouts and address response
issues.
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250831-usb-v2-1-00b9c0559733@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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clk-for-6.18
Merge the MSM8937 global clock controller binding through a topic branch
to allow merging the constants into the DeviceTree branch as well.
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Add device tree bindings for the global clock controller on Qualcomm
MSM8937 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20250903-msm8937-v9-1-a097c91c5801@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add devicetree binding document and related header file for
Amlogic S6 S7 S7D secure power domains.
Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250822-pm-s6-s7-s7d-v1-1-82e3f3aff327@amlogic.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add clock definitions for Ethernet (ETCLK A-E) to both R9A09G077 and
R9A09G087 SoCs. These definitions are required for describing Ethernet
devices in DT.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250904071954.3176806-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add device tree bindings for global clock controller on Glymur SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe and USB.
Add this to the TCSR clock controller binding together with identifiers
for the clocks.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-2-01b8c8681bcd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the device tree bindings for the display clock controller which are
required on Qualcomm Glymur SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com
[bjorn: Dropped unnecessary include in DT example]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Declare the positional index for the RP1 MIPI clocks.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/c20066500908db854aa4816b40e956296bab526a.1750714412.git.andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Add a clock id for mipi dsi reference clock, mipi dsi node used it.
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250831104855.45883-4-cn.liweihao@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Extend the existing Tegra186 GPIO controller device tree bindings with
support for the GPIO controller found on Tegra256. The number of pins is
slightly different, but the programming model remains the same
Add a new header, include/dt-bindings/gpio/tegra256-gpio.h,
that defines port IDs as well as the TEGRA256_MAIN_GPIO() helper,
both of which are used in conjunction to create a unique specifier
for each pin. The OS can reconstruct the port ID and pin from
these values to determine the register region for the corresponding
GPIO. However, the OS does not use the macro definitions in this file.
The symbolic names help associate these GPIO specifiers with the names
used in the technical documentation available for the chip.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250823055420.24664-1-pshete@nvidia.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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Add dt-schema for Axis ARTPEC-8 SoC clock controller.
The Clock Management Unit (CMU) has a top-level block CMU_CMU
which generates clocks for other blocks.
Add device-tree binding definitions for following CMU blocks:
- CMU_CMU
- CMU_BUS
- CMU_CORE
- CMU_CPUCL
- CMU_FSYS
- CMU_IMEM
- CMU_PERI
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add missing clock definitions for DPU and CMUREF.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-4-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In order to use the virtual clock SSPAx_I2S_BCLK in the device tree and
register it in the driver, this patch introduces the macro definition.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Link: https://lore.kernel.org/r/20250811-k1-clk-i2s-v5-1-ebadd06e1e91@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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'20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-1-c5a8af040093@yandex.ru' into clk-for-6.18
Merge the addition of a few missing clock defines for the SDM660 global
clock controller, in order to allow them to be used in the DeviceTree
branch as well.
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Add defines for the missing clocks, which are required to power up the
related remote processors.
Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-1-c5a8af040093@yandex.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Some of the Qualcomm RPM PD controllers use a common set of indices for
power domains. Add generic indices for Qualcomm RPM power domain
controllers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20250718-rework-rpmhpd-rpmpd-v1-3-eedca108e540@oss.qualcomm.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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After removing RPMh PD indices, it becomes obvious that several entries
don't follow the alphabetic sorting order. Move them in order to keep
the file sorted.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20250718-rework-rpmhpd-rpmpd-v1-2-eedca108e540@oss.qualcomm.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Historically both RPM and RPMh domain definitions were a part of the
same, qcom-rpmpd.h header. Now as we have a separate header for RPMh
definitions, qcom,rpmhpd.h, move all RPMh power domain definitions to
that header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20250718-rework-rpmhpd-rpmpd-v1-1-eedca108e540@oss.qualcomm.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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CAM_CSI block has ACLK, PCLK and PLL clocks. PCLK id is already
assigned. To use PCLK and PLL clock in driver add id macro for CAM_CSI_PLL
and CAM_CSI_PCLK.
Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
Link: https://lore.kernel.org/r/20250814140943.22531-2-inbaraj.e@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Glymur SoC
Document the RPMh Network-On-Chip Interconnect in Glymur platform.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250814-glymur-icc-v2-1-596cca6b6015@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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VOSYS contains more resets for a display pipeline, includes ones for the
display controller (called DPU in the manual), the HDMI controller and 2
MIPI DSI controllers.
Allocate IDs for these resets in the dt binding header file.
Now all peripheral related VOSYS reset controls are here, only the bus
matrix / IOPMP ones are missing, which shouldn't be messed with.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250813081716.2181843-2-uwu@icenowy.me
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Merge the IPQ5424 application subsystem clock binding, in order to get
access to the necessary clock constants for CPUfreq.
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into clk-for-6.18
Merge the addition of reset constants to the SC7280 display clock
controller binding through a topic branch to allow it to be included in
the DeviceTree branch as well.
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Like other platforms the sc7280 display clock controller provides a
couple of resets, add the defines to allow referring to them.
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250811-sc7280-mdss-reset-v1-1-83ceff1d48de@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document the pin and GPIO controller IP for the Renesas RZ/T2H
(R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI header
file used by both the bindings and the driver.
The RZ/T2H SoC supports 729 pins, while RZ/N2H supports 576 pins.
Both share the same controller architecture; separate compatible strings
are added for each SoC to distinguish them.
Co-developed-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250808133017.2053637-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add the USB clock (USB_CLK) definition for the Renesas RZ/T2H
(R9A09G077) and RZ/N2H (R9A09G087) SoCs. USB_CLK is used as the
reference clock for USB PHY layer.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250804202643.3967484-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Nothing stands out, apart from maybe the interesting Eswin EIC7700, a
RISC-V SoC I've never seen before.
Core changes:
- Open code PINCTRL_FUNCTION_DESC() instead of defining a complex
macro only used in one place
- Add pinmux_generic_add_pinfunction() helper and use this in a few
drivers
New drivers:
- Amlogic S7, S7D and S6 pin control support
- Eswin EIC7700 pin control support
- Qualcomm PMIV0104, PM7550 and Milos pin control support
Because of unhelpful numbering schemes, the Qualcomm driver now
needs to start to rely on SoC codenames
- STM32 HDP pin control support
- Mediatek MT8189 pin control support
Improvements:
- Switch remaining pin control drivers over to the new GPIO set
callback that provides a return value
- Support RSVD (reserved) pins in the STM32 driver
- Move many fixed assignments over to pinctrl_desc definitions
- Handle multiple TLMM regions in the Qualcomm driver"
* tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
pinctrl: mediatek: Add pinctrl driver for mt8189
dt-bindings: pinctrl: mediatek: Add support for mt8189
pinctrl: aspeed-g6: Add PCIe RC PERST pin group
pinctrl: ingenic: use pinmux_generic_add_pinfunction()
pinctrl: keembay: use pinmux_generic_add_pinfunction()
pinctrl: mediatek: moore: use pinmux_generic_add_pinfunction()
pinctrl: airoha: use pinmux_generic_add_pinfunction()
pinctrl: equilibrium: use pinmux_generic_add_pinfunction()
pinctrl: provide pinmux_generic_add_pinfunction()
pinctrl: pinmux: open-code PINCTRL_FUNCTION_DESC()
pinctrl: ma35: use new GPIO line value setter callbacks
MAINTAINERS: add Clément Le Goffic as STM32 HDP maintainer
pinctrl: stm32: Introduce HDP driver
dt-bindings: pinctrl: stm32: Introduce HDP
pinctrl: qcom: Add Milos pinctrl driver
dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
pinctrl: qcom: spmi: Add PM7550
dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
pinctrl: qcom: spmi: Add PMIV0104
dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
...
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This is the usual collection of primarily clk driver updates.
The big part of the diff is all the new Qualcomm clk drivers added for
a few SoCs they're working on. The other two vendors with significant
work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
to existing drivers and supports some new SoCs while Amlogic is
starting a significant refactoring to simplify their code.
The core framework gained a pair of helpers to get the 'struct device'
or 'struct device_node' associated with a 'struct clk_hw'. Some
associated KUnit tests were added for these simple helpers as well.
Beyond that core change there are lots of little fixes throughout the
clk drivers for the stuff we see every day, wrong clk driver data that
affects tree topology or supported frequencies, etc. They're not found
until the clks are actually used by some consumer device driver.
New Drivers:
- Global, display, gpu, video, camera, tcsr, and rpmh clock
controller for the Qualcomm Milos SoC
- Camera, display, GPU, and video clock controllers for Qualcomm
QCS615
- Video clock controller driver for Qualcomm SM6350
- Camera clock controller driver for Qualcomm SC8180X
- I3C clocks and resets on Renesas RZ/G3E
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/V2H(P) and RZ/V2N
- SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
- SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
- Ethernet clocks and resets on Renesas RZ/G3E
- Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
(R9A09G087) SoCs
- Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
- Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
RZ/V2N
Updates:
- Support atomic PWMs in the PWM clk driver
- clk_hw_get_dev() and clk_hw_get_of_node() helpers
- Replace round_rate() with determine_rate() in various clk drivers
- Convert clk DT bindings to DT schema format for DT validation
- Various clk driver cleanups and refactorings from static analysis
tools and possibly real humans
- A lot of little fixes here and there to things like clk tree
topology, missing frequencies, flagging clks as critical, etc"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
clk: clocking-wizard: Fix the round rate handling for versal
clk: Fix typos
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
clk: tegra: periph: Make tegra_clk_periph_ops static
clk: tegra: periph: Fix error handling and resolve unsigned compare warning
clk: imx: scu: convert from round_rate() to determine_rate()
clk: imx: pllv4: convert from round_rate() to determine_rate()
clk: imx: pllv3: convert from round_rate() to determine_rate()
clk: imx: pllv2: convert from round_rate() to determine_rate()
clk: imx: pll14xx: convert from round_rate() to determine_rate()
clk: imx: pfd: convert from round_rate() to determine_rate()
clk: imx: frac-pll: convert from round_rate() to determine_rate()
clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
clk: imx: fixup-div: convert from round_rate() to determine_rate()
clk: imx: cpu: convert from round_rate() to determine_rate()
clk: imx: busy: convert from round_rate() to determine_rate()
clk: imx: composite-93: remove round_rate() in favor of determine_rate()
clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
...
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Resolve conflicts with i.MX95 changes 88768d6f8c13 ("clk:
imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx
and aacc875a448d ("clk: imx: Fix an out-of-bounds access in
dispmix_csr_clk_dev_data") in clk-fixes.
* clk-fixes:
clk: sunxi-ng: v3s: Fix TCON clock parents
clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
clk: sunxi-ng: v3s: Fix CSI SCLK clock name
dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
clk: scmi: Handle case where child clocks are initialized before their parents
clk: sunxi-ng: a523: Mark MBUS clock as critical
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Pull drm updates from Dave Airlie:
"Highlights:
- Intel xe enable Panthor Lake, started adding WildCat Lake
- amdgpu has a bunch of reset improvments along with the usual IP
updates
- msm got VM_BIND support which is important for vulkan sparse memory
- more drm_panic users
- gpusvm common code to handle a bunch of core SVM work outside
drivers.
Detail summary:
Changes outside drm subdirectory:
- 'shrink_shmem_memory()' for better shmem/hibernate interaction
- Rust support infrastructure:
- make ETIMEDOUT available
- add size constants up to SZ_2G
- add DMA coherent allocation bindings
- mtd driver for Intel GPU non-volatile storage
- i2c designware quirk for Intel xe
core:
- atomic helpers: tune enable/disable sequences
- add task info to wedge API
- refactor EDID quirks
- connector: move HDR sink to drm_display_info
- fourcc: half-float and 32-bit float formats
- mode_config: pass format info to simplify
dma-buf:
- heaps: Give CMA heap a stable name
ci:
- add device tree validation and kunit
displayport:
- change AUX DPCD access probe address
- add quirk for DPCD probe
- add panel replay definitions
- backlight control helpers
fbdev:
- make CONFIG_FIRMWARE_EDID available on all arches
fence:
- fix UAF issues
format-helper:
- improve tests
gpusvm:
- introduce devmem only flag for allocation
- add timeslicing support to GPU SVM
ttm:
- improve eviction
sched:
- tracing improvements
- kunit improvements
- memory leak fixes
- reset handling improvements
color mgmt:
- add hardware gamma LUT handling helpers
bridge:
- add destroy hook
- switch to reference counted drm_bridge allocations
- tc358767: convert to devm_drm_bridge_alloc
- improve CEC handling
panel:
- switch to reference counter drm_panel allocations
- fwnode panel lookup
- Huiling hl055fhv028c support
- Raspberry Pi 7" 720x1280 support
- edp: KDC KD116N3730A05, N160JCE-ELL CMN, N116BCJ-EAK
- simple: AUO P238HAN01
- st7701: Winstar wf40eswaa6mnn0
- visionox: rm69299-shift
- Renesas R61307, Renesas R69328 support
- DJN HX83112B
hdmi:
- add CEC handling
- YUV420 output support
xe:
- WildCat Lake support
- Enable PanthorLake by default
- mark BMG as SRIOV capable
- update firmware recommendations
- Expose media OA units
- aux-bux support for non-volatile memory
- MTD intel-dg driver for non-volatile memory
- Expose fan control and voltage regulator in sysfs
- restructure migration for multi-device
- Restore GuC submit UAF fix
- make GEM shrinker drm managed
- SRIOV VF Post-migration recovery of GGTT nodes
- W/A additions/reworks
- Prefetch support for svm ranges
- Don't allocate managed BO for each policy change
- HWMON fixes for BMG
- Create LRC BO without VM
- PCI ID updates
- make SLPC debugfs files optional
- rework eviction rejection of bound external BOs
- consolidate PAT programming logic for pre/post Xe2
- init changes for flicker-free boot
- Enable GuC Dynamic Inhibit Context switch
i915:
- drm_panic support for i915/xe
- initial flip queue off by default for LNL/PNL
- Wildcat Lake Display support
- Support for DSC fractional link bpp
- Support for simultaneous Panel Replay and Adaptive sync
- Support for PTL+ double buffer LUT
- initial PIPEDMC event handling
- drm_panel_follower support
- DPLL interface renames
- allocate struct intel_display dynamically
- flip queue preperation
- abstract DRAM detection better
- avoid GuC scheduling stalls
- remove DG1 force probe requirement
- fix MEI interrupt handler on RT kernels
- use backlight control helpers for eDP
- more shared display code refactoring
amdgpu:
- add userq slot to INFO ioctl
- SR-IOV hibernation support
- Suspend improvements
- Backlight improvements
- Use scaling for non-native eDP modes
- cleaner shader updates for GC 9.x
- Remove fence slab
- SDMA fw checks for userq support
- RAS updates
- DMCUB updates
- DP tunneling fixes
- Display idle D3 support
- Per queue reset improvements
- initial smartmux support
amdkfd:
- enable KFD on loongarch
- mtype fix for ext coherent system memory
radeon:
- CS validation additional GL extensions
- drop console lock during suspend/resume
- bump driver version
msm:
- VM BIND support
- CI: infrastructure updates
- UBWC single source of truth
- decouple GPU and KMS support
- DP: rework I/O accessors
- DPU: SM8750 support
- DSI: SM8750 support
- GPU: X1-45 support and speedbin support for X1-85
- MDSS: SM8750 support
nova:
- register! macro improvements
- DMA object abstraction
- VBIOS parser + fwsec lookup
- sysmem flush page support
- falcon: generic falcon boot code and HAL
- FWSEC-FRTS: fb setup and load/execute
ivpu:
- Add Wildcat Lake support
- Add turbo flag
ast:
- improve hardware generations implementation
imx:
- IMX8qxq Display Controller support
lima:
- Rockchip RK3528 GPU support
nouveau:
- fence handling cleanup
panfrost:
- MT8370 support
- bo labeling
- 64-bit register access
qaic:
- add RAS support
rockchip:
- convert inno_hdmi to a bridge
rz-du:
- add RZ/V2H(P) support
- MIPI-DSI DCS support
sitronix:
- ST7567 support
sun4i:
- add H616 support
tidss:
- add TI AM62L support
- AM65x OLDI bridge support
bochs:
- drm panic support
vkms:
- YUV and R* format support
- use faux device
vmwgfx:
- fence improvements
hyperv:
- move out of simple
- add drm_panic support"
* tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel: (1479 commits)
drm/tidss: oldi: convert to devm_drm_bridge_alloc() API
drm/tidss: encoder: convert to devm_drm_bridge_alloc()
drm/amdgpu: move reset support type checks into the caller
drm/amdgpu/sdma7: re-emit unprocessed state on ring reset
drm/amdgpu/sdma6: re-emit unprocessed state on ring reset
drm/amdgpu/sdma5.2: re-emit unprocessed state on ring reset
drm/amdgpu/sdma5: re-emit unprocessed state on ring reset
drm/amdgpu/gfx12: re-emit unprocessed state on ring reset
drm/amdgpu/gfx11: re-emit unprocessed state on ring reset
drm/amdgpu/gfx10: re-emit unprocessed state on ring reset
drm/amdgpu/gfx9.4.3: re-emit unprocessed state on kcq reset
drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset
drm/amdgpu: Add WARN_ON to the resource clear function
drm/amd/pm: Use cached metrics data on SMUv13.0.6
drm/amd/pm: Use cached data for min/max clocks
gpu: nova-core: fix bounds check in PmuLookupTableEntry::new
drm/amdgpu: Replace HQD terminology with slots naming
drm/amdgpu: Add user queue instance count in HW IP info
drm/amd/amdgpu: Add helper functions for isp buffers
drm/amd/amdgpu: Initialize swnode for ISP MFD device
...
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
Pull networking updates from Jakub Kicinski:
"Core & protocols:
- Wrap datapath globals into net_aligned_data, to avoid false sharing
- Preserve MSG_ZEROCOPY in forwarding (e.g. out of a container)
- Add SO_INQ and SCM_INQ support to AF_UNIX
- Add SIOCINQ support to AF_VSOCK
- Add TCP_MAXSEG sockopt to MPTCP
- Add IPv6 force_forwarding sysctl to enable forwarding per interface
- Make TCP validation of whether packet fully fits in the receive
window and the rcv_buf more strict. With increased use of HW
aggregation a single "packet" can be multiple 100s of kB
- Add MSG_MORE flag to optimize large TCP transmissions via sockmap,
improves latency up to 33% for sockmap users
- Convert TCP send queue handling from tasklet to BH workque
- Improve BPF iteration over TCP sockets to see each socket exactly
once
- Remove obsolete and unused TCP RFC3517/RFC6675 loss recovery code
- Support enabling kernel threads for NAPI processing on per-NAPI
instance basis rather than a whole device. Fully stop the kernel
NAPI thread when threaded NAPI gets disabled. Previously thread
would stick around until ifdown due to tricky synchronization
- Allow multicast routing to take effect on locally-generated packets
- Add output interface argument for End.X in segment routing
- MCTP: add support for gateway routing, improve bind() handling
- Don't require rtnl_lock when fetching an IPv6 neighbor over Netlink
- Add a new neighbor flag ("extern_valid"), which cedes refresh
responsibilities to userspace. This is needed for EVPN multi-homing
where a neighbor entry for a multi-homed host needs to be synced
across all the VTEPs among which the host is multi-homed
- Support NUD_PERMANENT for proxy neighbor entries
- Add a new queuing discipline for IETF RFC9332 DualQ Coupled AQM
- Add sequence numbers to netconsole messages. Unregister
netconsole's console when all net targets are removed. Code
refactoring. Add a number of selftests
- Align IPSec inbound SA lookup to RFC 4301. Only SPI and protocol
should be used for an inbound SA lookup
- Support inspecting ref_tracker state via DebugFS
- Don't force bonding advertisement frames tx to ~333 ms boundaries.
Add broadcast_neighbor option to send ARP/ND on all bonded links
- Allow providing upcall pid for the 'execute' command in openvswitch
- Remove DCCP support from Netfilter's conntrack
- Disallow multiple packet duplications in the queuing layer
- Prevent use of deprecated iptables code on PREEMPT_RT
Driver API:
- Support RSS and hashing configuration over ethtool Netlink
- Add dedicated ethtool callbacks for getting and setting hashing
fields
- Add support for power budget evaluation strategy in PSE /
Power-over-Ethernet. Generate Netlink events for overcurrent etc
- Support DPLL phase offset monitoring across all device inputs.
Support providing clock reference and SYNC over separate DPLL
inputs
- Support traffic classes in devlink rate API for bandwidth
management
- Remove rtnl_lock dependency from UDP tunnel port configuration
Device drivers:
- Add a new Broadcom driver for 800G Ethernet (bnge)
- Add a standalone driver for Microchip ZL3073x DPLL
- Remove IBM's NETIUCV device driver
- Ethernet high-speed NICs:
- Broadcom (bnxt):
- support zero-copy Tx of DMABUF memory
- take page size into account for page pool recycling rings
- Intel (100G, ice, idpf):
- idpf: XDP and AF_XDP support preparations
- idpf: add flow steering
- add link_down_events statistic
- clean up the TSPLL code
- preparations for live VM migration
- nVidia/Mellanox:
- support zero-copy Rx/Tx interfaces (DMABUF and io_uring)
- optimize context memory usage for matchers
- expose serial numbers in devlink info
- support PCIe congestion metrics
- Meta (fbnic):
- add 25G, 50G, and 100G link modes to phylink
- support dumping FW logs
- Marvell/Cavium:
- support for CN20K generation of the Octeon chips
- Amazon:
- add HW clock (without timestamping, just hypervisor time access)
- Ethernet virtual:
- VirtIO net:
- support segmentation of UDP-tunnel-encapsulated packets
- Google (gve):
- support packet timestamping and clock synchronization
- Microsoft vNIC:
- add handler for device-originated servicing events
- allow dynamic MSI-X vector allocation
- support Tx bandwidth clamping
- Ethernet NICs consumer, and embedded:
- AMD:
- amd-xgbe: hardware timestamping and PTP clock support
- Broadcom integrated MACs (bcmgenet, bcmasp):
- use napi_complete_done() return value to support NAPI polling
- add support for re-starting auto-negotiation
- Broadcom switches (b53):
- support BCM5325 switches
- add bcm63xx EPHY power control
- Synopsys (stmmac):
- lots of code refactoring and cleanups
- TI:
- icssg-prueth: read firmware-names from device tree
- icssg: PRP offload support
- Microchip:
- lan78xx: convert to PHYLINK for improved PHY and MAC management
- ksz: add KSZ8463 switch support
- Intel:
- support similar queue priority scheme in multi-queue and
time-sensitive networking (taprio)
- support packet pre-emption in both
- RealTek (r8169):
- enable EEE at 5Gbps on RTL8126
- Airoha:
- add PPPoE offload support
- MDIO bus controller for Airoha AN7583
- Ethernet PHYs:
- support for the IPQ5018 internal GE PHY
- micrel KSZ9477 switch-integrated PHYs:
- add MDI/MDI-X control support
- add RX error counters
- add cable test support
- add Signal Quality Indicator (SQI) reporting
- dp83tg720: improve reset handling and reduce link recovery time
- support bcm54811 (and its MII-Lite interface type)
- air_en8811h: support resume/suspend
- support PHY counters for QCA807x and QCA808x
- support WoL for QCA807x
- CAN drivers:
- rcar_canfd: support for Transceiver Delay Compensation
- kvaser: report FW versions via devlink dev info
- WiFi:
- extended regulatory info support (6 GHz)
- add statistics and beacon monitor for Multi-Link Operation (MLO)
- support S1G aggregation, improve S1G support
- add Radio Measurement action fields
- support per-radio RTS threshold
- some work around how FIPS affects wifi, which was wrong (RC4 is
used by TKIP, not only WEP)
- improvements for unsolicited probe response handling
- WiFi drivers:
- RealTek (rtw88):
- IBSS mode for SDIO devices
- RealTek (rtw89):
- BT coexistence for MLO/WiFi7
- concurrent station + P2P support
- support for USB devices RTL8851BU/RTL8852BU
- Intel (iwlwifi):
- use embedded PNVM in (to be released) FW images to fix
compatibility issues
- many cleanups (unused FW APIs, PCIe code, WoWLAN)
- some FIPS interoperability
- MediaTek (mt76):
- firmware recovery improvements
- more MLO work
- Qualcomm/Atheros (ath12k):
- fix scan on multi-radio devices
- more EHT/Wi-Fi 7 features
- encapsulation/decapsulation offload
- Broadcom (brcm80211):
- support SDIO 43751 device
- Bluetooth:
- hci_event: add support for handling LE BIG Sync Lost event
- ISO: add socket option to report packet seqnum via CMSG
- ISO: support SCM_TIMESTAMPING for ISO TS
- Bluetooth drivers:
- intel_pcie: support Function Level Reset
- nxpuart: add support for 4M baudrate
- nxpuart: implement powerup sequence, reset, FW dump, and FW loading"
* tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1742 commits)
dpll: zl3073x: Fix build failure
selftests: bpf: fix legacy netfilter options
ipv6: annotate data-races around rt->fib6_nsiblings
ipv6: fix possible infinite loop in fib6_info_uses_dev()
ipv6: prevent infinite loop in rt6_nlmsg_size()
ipv6: add a retry logic in net6_rt_notify()
vrf: Drop existing dst reference in vrf_ip6_input_dst
net/sched: taprio: align entry index attr validation with mqprio
net: fsl_pq_mdio: use dev_err_probe
selftests: rtnetlink.sh: remove esp4_offload after test
vsock: remove unnecessary null check in vsock_getname()
igb: xsk: solve negative overflow of nb_pkts in zerocopy mode
stmmac: xsk: fix negative overflow of budget in zerocopy mode
dt-bindings: ieee802154: Convert at86rf230.txt yaml format
net: dsa: microchip: Disable PTP function of KSZ8463
net: dsa: microchip: Setup fiber ports for KSZ8463
net: dsa: microchip: Write switch MAC address differently for KSZ8463
net: dsa: microchip: Use different registers for KSZ8463
net: dsa: microchip: Add KSZ8463 switch support to KSZ DSA driver
dt-bindings: net: dsa: microchip: Add KSZ8463 switch support
...
|
|
'clk-qcom' into clk-next
* clk-rockchip:
clk: rockchip: rk3568: Add PLL rate for 132MHz
* clk-thead:
clk: thead: th1520-ap: Describe mux clocks with clk_mux
clk: thead: th1520-ap: Correctly refer the parent of osc_12m
clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED
* clk-microchip:
clk: at91: sam9x7: update pll clk ranges
* clk-imx:
MAINTAINERS: Update i.MX Clock Entry
clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
clk: imx95-blk-ctl: Fix synchronous abort
dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
* clk-qcom: (65 commits)
dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom: Remove double colon from description
clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Video Clock Controller
clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos
dt-bindings: clock: qcom: document the Milos GPU Clock Controller
clk: qcom: Add Display Clock controller (DISPCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Display Clock Controller
clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Camera Clock Controller
clk: qcom: Add Global Clock controller (GCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Global Clock Controller
clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe
clk: qcom: gcc-x1e80100: Add missing video resets
dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC
...
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and 'clk-amlogic' into clk-next
* clk-renesas: (42 commits)
clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
clk: renesas: r9a09g057: Add XSPI clock/reset
clk: renesas: r9a09g056: Add XSPI clock/reset
clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
clk: renesas: r9a09g057: Add support for xspi mux and divider
clk: renesas: r9a09g056: Add support for xspi mux and divider
clk: renesas: r9a09g077: Add RIIC module clocks
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
clk: renesas: r9a09g057: Add entries for the RSPIs
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
clk: renesas: rzv2h: Add missing include file
clk: renesas: rzv2h: Use devm_kmemdup_array()
clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
clk: renesas: r9a09g077: Add PCLKL core clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
...
* clk-samsung:
clk: samsung: exynosautov920: add block hsi2 clock support
dt-bindings: clock: exynosautov920: add hsi2 clock definitions
dt-bindings: clock: exynosautov920: sort clock definitions
clk: samsung: exynos850: fix a comment
clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD
* clk-spacemit:
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: mark K1 pll1_d8 as critical
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
* clk-allwinner:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
* clk-amlogic:
clk: amlogic: s4: remove unused data
clk: amlogic: drop clk_regmap tables
clk: amlogic: get regmap with clk_regmap_init
clk: amlogic: remove unnecessary headers
clk: amlogic: axg-audio: use the auxiliary reset driver
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"These five newly supported chips come with both devicetree
descriptions and the changes to wire them up to the build system for
easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before
the entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor. It
uses four in-order AX45MP cores, which is the midrange product from
Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one of
the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can be
used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V and
Arm cores that can run Linux. This was already supported for RISC-V
but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window"
* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Changes are all over the place, but very little sticks out as
noteworthy.
There is a new misc driver for the Raspberry Pi 5's RP1 multifunction
I/O chip, along with hooking it up to the pinctrl and clk frameworks.
The reset controller and memory subsystems have mainly small updates,
but there are two new reset drivers for the K230 and VC1800B SoCs, and
new memory driver support for Tegra264.
The ARM SMCCC and SCMI firmware drivers gain a few more features that
should help them be supported across more environments. Similarly, the
SoC specific firmware on Tegra and Qualcomm get minor enhancements and
chip support.
In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an
overhaul for code robustness, the Tegra and Qualcomm and NXP drivers
grow to support more chips, while the Hisilicon, Mediatek and Renesas
drivers see mostly janitorial fixes"
* tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (100 commits)
bus: del unnecessary init var
soc: fsl: qe: convert set_multiple() to returning an integer
pinctrl: rp1: use new GPIO line value setter callbacks
soc: hisilicon: kunpeng_hccs: Fix incorrect log information
dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
soc: qcom: socinfo: Add support to retrieve APPSBL build details
soc: qcom: pmic_glink: fix OF node leak
soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs
soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs
soc: qcom: socinfo: Add SoC IDs for SM7635 family
dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
firmware: qcom: scm: request the waitqueue irq *after* initializing SCM
firmware: qcom: scm: initialize tzmem before marking SCM as available
firmware: qcom: scm: take struct device as argument in SHM bridge enable
firmware: qcom: scm: remove unused arguments from SHM bridge routines
soc: qcom: rpmh-rsc: Add RSC version 4 support
memory: tegra: Add Tegra264 MC and EMC support
firmware: tegra: bpmp: Fix build failure for tegra264-only config
...
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Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now
- exynos2200 is a recent high-end mobile phone chip used in a few
Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it
There are five more chips in a separate branch, as those are new chip
families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly added
machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
sg2042
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5"
* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
riscv: dts: sophgo: fix mdio node name for CV180X
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
riscv: dts: sophgo: add ethernet GMAC device for sg2042
riscv: dts: sophgo: Enable ethernet device for Huashan Pi
riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
riscv: dts: sophgo: Add ethernet device for cv18xx
riscv: dts: sophgo: sg2044: add pmu configuration
riscv: dts: sophgo: sg2044: add ziccrse extension
riscv: dts: sophgo: add zfh for sg2042
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
...
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc / IIO / other driver updates from Greg KH:
"Here is the big set of char/misc/iio and other smaller driver
subsystems for 6.17-rc1. It's a big set this time around, with the
huge majority being in the iio subsystem with new drivers and dts
files being added there.
Highlights include:
- IIO driver updates, additions, and changes making more code const
and cleaning up some init logic
- bus_type constant conversion changes
- misc device test functions added
- rust miscdevice minor fixup
- unused function removals for some drivers
- mei driver updates
- mhi driver updates
- interconnect driver updates
- Android binder updates and test infrastructure added
- small cdx driver updates
- small comedi fixes
- small nvmem driver updates
- small pps driver updates
- some acrn virt driver fixes for printk messages
- other small driver updates
All of these have been in linux-next with no reported issues"
* tag 'char-misc-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (292 commits)
binder: Use seq_buf in binder_alloc kunit tests
binder: Add copyright notice to new kunit files
misc: ti_fpc202: Switch to of_fwnode_handle()
bus: moxtet: Use dev_fwnode()
pc104: move PC104 option to drivers/Kconfig
drivers: virt: acrn: Don't use %pK through printk
comedi: fix race between polling and detaching
interconnect: qcom: Add Milos interconnect provider driver
dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
mei: more prints with client prefix
mei: bus: use cldev in prints
bus: mhi: host: pci_generic: Add Telit FN990B40 modem support
bus: mhi: host: Detect events pointing to unexpected TREs
bus: mhi: host: pci_generic: Add Foxconn T99W696 modem
bus: mhi: host: Use str_true_false() helper
bus: mhi: host: pci_generic: Add support for EM929x and set MRU to 32768 for better performance.
bus: mhi: host: Fix endianness of BHI vector table
bus: mhi: host: pci_generic: Disable runtime PM for QDU100
bus: mhi: host: pci_generic: Fix the modem name of Foxconn T99W640
dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio'
...
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
Pull regulator updates from Mark Brown:
"The big change in this release is the addition of Rust bindings from
Daniel Almeida, allowing fairly basic consumer use with support for
enable and voltage setting operations. This should be good for the
vast majority of consumers.
Otherwise it's been quite quiet, a few new devices supported, plus
some cleanups and fixes.
Summary:
- Basic Rust bindings
- A fix for making large voltage changes on regulators where we limit
the size of voltage change we will do in one step, previously we
just got as close as we could in one step
- Cleanups of our usage of the PM autosuspend functions, this pulls
in some PM core changes on a shared tag
- Mode setting support for PCA9450
- Support for Mediatek MT6893 and MT8196 DVFSRC, Qualcomm PM7550 and
PMR735B, Raspberry Pi displays and TI TPS652G1
The TI driver pulls in the MFD portion of the support for the device
and the pinctrl driver which was in the same tag"
* tag 'regulator-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: (40 commits)
regulator: mt6370: Fix spelling mistake in mt6370_regualtor_register
regulator: Kconfig: Fix spelling mistake "regualtor" -> "regulator"
regulator: core: repeat voltage setting request for stepped regulators
regulator: rt6160: Add rt6166 vout min_uV setting for compatible
MAINTAINERS: add regulator.rs to the regulator API entry
rust: regulator: add a bare minimum regulator abstraction
regulator: tps6286x-regulator: Fix a copy & paste error
regulator: qcom-rpmh: add support for pm7550 regulators
regulator: qcom-rpmh: add support for pmr735b regulators
regulator: dt-bindings: qcom,rpmh: Add PMR735B compatible
regulator: dt-bindings: qcom,rpmh: Add PM7550 compatible
regulator: tps6594-regulator: Add TI TPS652G1 PMIC regulators
regulator: tps6594-regulator: refactor variant descriptions
regulator: tps6594-regulator: remove hardcoded buck config
regulator: tps6594-regulator: remove interrupt_count
dt-bindings: mfd: ti,tps6594: Add TI TPS652G1 PMIC
pinctrl: pinctrl-tps6594: Add TPS652G1 PMIC pinctrl and GPIO
misc: tps6594-pfsm: Add TI TPS652G1 PMIC PFSM
mfd: tps6594: Add TI TPS652G1 support
regulator: sy8827n: make enable gpio NONEXCLUSIVE
...
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
More Qualcomm driver updates for v6.17
Fix race condition during SCM driver initialization, in relation to
tzmem and waitqueue irq handling,
Make the rpmh RSC driver support version 4 of the IP block.
Add SM7635 family and related PMICs to the socinfo driver. Also add
support for retrieving the bootloader build details.
* tag 'qcom-drivers-for-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
soc: qcom: socinfo: Add support to retrieve APPSBL build details
soc: qcom: pmic_glink: fix OF node leak
soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs
soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs
soc: qcom: socinfo: Add SoC IDs for SM7635 family
dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
firmware: qcom: scm: request the waitqueue irq *after* initializing SCM
firmware: qcom: scm: initialize tzmem before marking SCM as available
firmware: qcom: scm: take struct device as argument in SHM bridge enable
firmware: qcom: scm: remove unused arguments from SHM bridge routines
soc: qcom: rpmh-rsc: Add RSC version 4 support
Link: https://lore.kernel.org/r/20250720030743.285440-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 6.17
This pull request contains the interconnect changes for the 6.17-rc1
merge window. It contains only driver changes.
Driver changes:
- SC8180X and SC8280XP driver fixes
- Add new driver for the Qualcomm Milos SoC
- Add Support for EPSS L3 hardware in QCS8300 SoC
- DT bindings fixes and other cleanups
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-6.17-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: qcom: Add Milos interconnect provider driver
dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio'
dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
dt-bindings: interconnect: qcom: Remove double colon from description
interconnect: qcom: qcs615: Drop IP0 interconnects
interconnect: qcom: sc8180x: specify num_nodes
interconnect: qcom: sc8280xp: specify num_links for qnm_a1noc_cfg
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https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
memory: tegra: Updates for v6.17-rc1
Enable support for the memory and external memory controllers found on
Tegra264.
* tag 'tegra-for-6.17-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra: Add Tegra264 MC and EMC support
dt-bindings: memory: tegra: Add Tegra264 support
Link: https://lore.kernel.org/r/20250711220943.2389322-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.17
79b896e7da7e arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
6516961352a1 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
The DB410c D3 camera mezzanine is converted to an overlay.
On MSM8976 SDC2 pinctrl definitions are introduced and BLSP DMA
controller is marked to be managed by another entity.
Add camera subsystem on the QCM2290 platform.
Add and enable remoteproc and related devices on QCS615.
Add and enable Video encoder/decoder on QCS8300 and SA8775P.
Also on SA8775P add CPU OPP tables for scaling DDR/L3 bandwidth based on
CPU frequency, add L3 interconnect definitions, DSI and video
encoder/decoder support.
Enable the SLPI remoteproc on SDM850-based Lenovo Yoga C630.
On SM6350, add the video clock controller, APR and some audio related
services.
Describe the camera subsystem on SM8550 and add Iris video
encoder/decoder node for SM8650.
On SM8750 introduce UFS and Soundwire support, enable these and describe
the sound hardware on MTP and QRD.
Add camera clock controller on SC8180X.
On X Elite, for the Dell XPS13, add WiFi and Bluetooth pwrseq and enable
the fingerprint sensor. For HP Omnibook X14 USB1 SS1 SBU mux and do
some misc cleanup.
Replace the thermal zones inherited from X Elite with X Plus-specific
ones.
Add missing interrupts and clean up unrelated clocks for PCIe
controllers across a variety of platforms.
* tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits)
arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts
arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts
arm64: dts: qcom: x1-asus-zenbook: support sound
arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes
arm64: dts: qcom: sm6115: add debug UART pins
arm64: dts: qcom: sm8650: add iris DT node
arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
arm64: dts: qcom: msm8976: Add sdc2 GPIOs
dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus
arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely
arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc
arm64: dts: qcom: sm8550: Add support for camss
arm64: dts: qcom: qcs615: disable the CTI device of the camera block
arm64: dts: qcom: qcs615-ride: enable remoteprocs
arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
arm64: dts: qcom: qcs615: Add IMEM and PIL info region
arm64: dts: qcom: qcs615: Add mproc node for SEMP2P
arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
arm64: dts: qcom: sc7180: Expand IMEM region
arm64: dts: qcom: sdm845: Expand IMEM region
...
Link: https://lore.kernel.org/r/20250716031059.76348-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner device tree changes for 6.17
This branch includes a change shared with the clk tree for adding
the missing PPU0 reset on the A523.
The PM domain DT binding immutable branch is also included, which
brings in v6.16-rc2, as well as PM domain bindings for other platforms.
Other changes include:
- RGB666 LCD pin definitions for the V3s PE pins and V3 PD pins
- node order fixes for the A523 dtsi
- UART1 pin definitions for A523
- Allwinner board DT binding cleanup
- EMAC support on A100/A133
- Enabled on the Liontron H-A133L board
- SID efuse, power controllers and GPU added for A523
- A523 GPU enabled on all existing boards
New boards:
- Xunlong OrangePi 4A with the Allwinner T527 SoC.
* tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
arm64: dts: allwinner: a523: enable Mali GPU for all boards
arm64: dts: allwinner: a523: add Mali GPU node
arm64: dts: allwinner: a523: Add power controller device nodes
dt-bindings: power: Add A523 PPU and PCK600 power controllers
arm64: dts: allwinner: A523: Add SID controller node
arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
arm64: dts: allwinner: a100: Add EMAC support
arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
dt-bindings: arm: sunxi: Combine board variants into enums
dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains
arm64: dts: allwinner: t527: Add OrangePi 4A board
arm64: dts: allwinner: a523: Add UART1 pins
arm64: dts: allwinner: a523: Move rgmii0 pins to correct location
arm64: dts: allwinner: a523: Move mmc nodes to correct position
dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board
ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition
ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
dt-bindings: rockchip: pmu: Add compatible for RK3528
...
Link: https://lore.kernel.org/r/aHaQFe3Lr8Qzyb1M@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into soc/dt
RISC-V SpacemiT DT changes for 6.17
- Add DMA translation buses
- Add PWM support
- Add Reset support
- Add eMMC node
* tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux:
riscv: dts: spacemit: Move eMMC under storage-bus for K1
riscv: dts: spacemit: Move UARTs under dma-bus for K1
riscv: dts: spacemit: Add DMA translation buses for K1
riscv: dts: spacemit: add pwm14_1 pinctrl setting
riscv: dts: spacemit: add PWM support for K1 SoC
riscv: dts: spacemit: add reset support for the K1 SoC
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
riscv: dts: spacemit: enable eMMC for K1 SoC
Link: https://lore.kernel.org/r/20250715014214-GYA540030@gentoo
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Updates for v6.17-rc1
Add Tegra264 compatible strings for some core components and extend
bindings where necessary to accomodate the new hardware generation. Also
document some new platforms, for both old and new chips.
* tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T
dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T
dt-bindings: Add Tegra264 clock and reset definitions
dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform
dt-bindings: rtc: tegra: Document Tegra264 RTC
dt-bindings: dma: Add Tegra264 compatible string
dt-bindings: misc: Document Tegra264 APBMISC compatible
dt-bindings: firmware: Document Tegra264 BPMP
dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
dt-bindings: tegra: pmc: Add Tegra264 compatible
dt-bindings: memory: tegra: Add Tegra264 support
Link: https://lore.kernel.org/r/20250711220943.2389322-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Qualcomm Milos SoC
Document the RPMh Network-On-Chip Interconnect of the Milos (e.g.
SM7635) SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250709-sm7635-icc-v3-1-c446203c3b3a@fairphone.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Patches from Peter Chen <peter.chen@cixtech.com>:
Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief
introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview
Currently, to run upstream kernel at Orion O6 board, you need to
use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs.
https://docs.radxa.com/en/orion/o6/bios/install-bios
In this series, we add initial SoC and board support for Kernel building.
Since mailbox is used for SCMI clock communication, mailbox driver is added
in this series for the minimum SoC support.
Patch 1-2: add dt-binding doc for CIX and its sky1 SoC
Patch 3: add Arm64 build support
Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol.
Patch 6: add Arm64 defconfig support
Patch 7-8: add initial dts support for SoC and Orion O6 board
Patch 9: add MAINTAINERS entry
* newsoc/cix-p1:
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
dt-bindings: mailbox: add cix,sky1-mbox
arm64: Kconfig: add ARCH_CIX for cix silicons
dt-bindings: arm: add CIX P1 (SKY1) SoC
dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add device tree bindings for the scmi clock id on
Cix sky1 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.17, round 1
Highlights:
----------
- MPU:
- STM32MP13:
-Add Ethernet MAC adress efuse support.
- STMP32MP15:
- Add stm32mp157f-DK2 board support. This board embedds the same
conectivity devices, DDR ... than stm32mp157c-dk2.
However there are two differences: STM32MP157F SoC which allows
overdrive OPP and the SCMI support for system features like
clocks and regulators.
- STM32MP25:
- Fix tick timer for low power use cases.
- Add timer support.
* tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
arm64: dts: st: remove empty line in stm32mp251.dtsi
arm64: dts: st: fix timer used for ticks
arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driver
ARM: dts: stm32: add stm32mp157f-dk2 board support
dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
arm64: defconfig: enable STM32 timers drivers
arm64: dts: st: add timer nodes on stm32mp257f-ev1
arm64: dts: st: add timer pins for stm32mp257f-ev1
arm64: dts: st: add timer nodes on stm32mp251
ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses
Link: https://lore.kernel.org/r/b3e3363b-1ea5-457c-b244-2cbe26f7d6e4@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.17 (take two)
- Add support for the Renesas Gray Hawk Single board with R-Car
V4M-7 (R8A779H2),
- Add eMMC and microSD expansion board support for the RZ/V2H and
RZ/V2N EVK development boards,
- Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC
Carrier-II EVK development board,
- Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK
development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g057: Add XSPI node
arm64: dts: renesas: r9a09g056: Add XSPI node
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target
arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
arm64: dts: renesas: Add Renesas R8A779H2 SoC support
arm64: dts: renesas: Factor out Gray Hawk Single board support
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into soc/drivers
This pull request contains Broadcom SoCs drivers updates for 6.17,
please pull the following:
- Andrea adds the RP1 clock, pinctrl/pinconf/gpio and misc driver to
bind them all
* tag 'arm-soc/for-6.17/drivers' of https://github.com/Broadcom/stblinux:
pinctrl: rp1: Implement RaspberryPi RP1 pinmux/pinconf support
misc: rp1: RaspberryPi RP1 misc driver
pinctrl: rp1: Implement RaspberryPi RP1 gpio support
clk: rp1: Add support for clocks provided by RP1
dt-bindings: clock: Add RaspberryPi RP1 clock bindings
Link: https://lore.kernel.org/r/20250630190216.1518354-4-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add i.MX94 LVDS/DISPLAY CSR compatible string.
Add clock index for the two CSRs.
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-1-c1b676ec13be@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Add bindings documentation for the Milos (e.g. SM7635) Video Clock
Controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock
Controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add bindings documentation for the Milos (e.g. SM7635) Display Clock
Controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add bindings documentation for the Milos (e.g. SM7635) Global Clock
Controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the missing video resets that are needed for the iris video codec.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-4-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add DT bindings for the Video clock on QCS615 platforms. Add the
relevant DT include definitions as well.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add DT bindings for the Display clock on QCS615 platforms. Add the
relevant DT include definitions as well.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add DT bindings for the Camera clock on QCS615 platforms. Add the
relevant DT include definitions as well.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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clk-for-6.17
Merge the IPQ5018 CMN PLL binding through a topic branch, to allow
merging the clock defines into DeviceTree branch as well.
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The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the SoC IDs of the 'volcano' family, namely SM7635, SM6650, SM6650P,
QCM6690 and QCS6690.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250625-sm7635-socinfo-v1-1-be09d5c697b8@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm into sunxi/dt-for-6.17
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The A523 PPU is likely the same kind of hardware seen on previous SoCs.
The A523 PCK600, as the name suggests, is likely a customized version
of ARM's PCK-600 power controller. Comparing the BSP driver against
ARM's PPU datasheet shows that the basic registers line up, but
Allwinner's hardware has some additional delay controls in the reserved
register range. As such it is likely not fully compatible with the
standard ARM version.
Document A523 PPU and PCK600 compatibles.
Also reorder the compatible string entries so they are grouped and
ordered by family first, then by SoC model.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20250712074021.805953-2-wens@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add a compatible and channel bindings for MediaTek's MT6373 PMIC,
featuring an Auxiliary ADC IP with 15 ADC channels for external
(SoC) temperatures and external voltage inputs.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250703141146.171431-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Add a compatible and channel bindings for MediaTek's MT6363 PMIC,
featuring an Auxiliary ADC IP with 15 ADC channels used for both
internal temperatures and voltages and for external voltage inputs.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250703141146.171431-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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The BPMP firmware on Tegra264 defines a set of IDs for clock and reset
resources. These are not enumerations but provided by hardware, and 0 is
a reserved value, hence the numbering starts at 1.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add bindings for the Memory Controller (MC) and External Memory
Controller (EMC) found on the Tegra264 SoC. Tegra264 SoC has a different
number of interrupt lines for MC sub-units: UCF_SOC, hub, hub common,
syncpoint and MC channel. The total number of interrupt lines is eight.
Update maxItems for MC interrupts accordingly.
This also adds a header containing the memory client ID definitions that
are used by the interconnects property in DT and the tegra_mc_client
table in the MC driver. These IDs are defined by the hardware, so the
numbering doesn't start at 0 and contains holes. Also added are the
stream IDs for various hardware blocks found on Tegra264. These are
allocated as blocks of 256 IDs and each block can be subdivided for
additional fine-grained isolation if needed.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
[treding@nvidia.com: add SMMU stream IDs, squash patches]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250709222147.3758356-2-thierry.reding@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The PMC found on Tegra264 is similar to the version in earlier chips but
some of the register offsets and bitfields differ, so add a specific
compatible string for this new generation.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250506133118.1011777-2-thierry.reding@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to
the ast2600-clock binding header. These are required for proper
reset control of the MAC1 and MAC2 ethernet controllers on the
AST2600 SoC.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://patch.msgid.link/20250709070809.2560688-3-jacky_chou@aspeedtech.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Update the RPMH level definitions to include TURBO_L5 corner.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/661840/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
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These bindings will be used for the SCMI voltage domain.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-3-5be0854a9299@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.
Fix the name in the driver, header and device-tree.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-By: Icenowy Zheng <uwu@icenowy.me>
Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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There are additional SpacemiT syscon CCUs whose registers control both
clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined
previously, these will (initially) support only resets. They do not
incorporate power domain functionality.
Previously the clock properties were required for all compatible nodes.
Make that requirement only apply to the three existing CCUs (APBC, APMU,
and MPMU), so that the new reset-only CCUs can go without specifying them.
Define the index values for resets associated with all SpacemiT K1
syscon nodes, including those with clocks already defined, as well as
the new ones (without clocks).
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250702113709.291748-2-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions
Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions
for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared
by driver and DT source files.
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Renesas RZ/T2H and RZ/N2H SDHI Clock DT Binding Definitions
SDHI clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and
RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
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Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add XSPI core clock definitions to the clock bindings for the Renesas
R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI
interface.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Introduces a reset controller driver for the Kendryte K230 SoC,
resposible for managing the reset functionality of the CPUs and
various sub-modules.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250613-k230-reset-v4-1-e5266d2be440@pigmoral.tech
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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In addition to GPIO synchronization, The AD7768-1 also supports
synchronization over SPI, which use is recommended when the GPIO
cannot provide a pulse synchronous with the base MCLK signal. It
consists of looping back the SYNC_OUT to the SYNC_IN pin and send
a command via SPI to trigger the synchronization.
Introduce the 'trigger-sources' property to enable SPI-based
synchronization via SYNC_OUT pin, along with additional optional
entries for GPIO3 and DRDY pins.
Also create #trigger-source-cells property to differentiate the trigger
sources provided by the ADC. To improve readability, create a
adi,ad7768-1.h header with the macros for the cell values.
While at it, add description to the interrupts property.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: David Lechner <dlechner@baylirbe.com>
Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Link: https://patch.msgid.link/713fd786010c75858700efaec8bb285274e7057e.1749569957.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 52dbf84857f0 ("dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250619171025.3359384-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Renesas RZ/N2H DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
SoC, shared by driver and DT source files.
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Renesas RZ/T2H PCLKL Clock DT Binding Definition
Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas
RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
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Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H
(R9A09G077) SoC. This clock is used by peripherals such as IIC, WDT,
and others.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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into clk-for-6.17
Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.
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The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.
Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the compatible string and power domains for RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250518220707.669515-2-jonas@kwiboo.se
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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