Questions tagged [verilog]
Verilog is a hardware description language (HDL) maintained by Accellera Systems Initiative and standardized as 'IEEE Standard 1364'.
41 questions
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Button Debounce in Verilog
I'm learning FPGA development, and this is my first Verilog module - a button bouncer using a state machine. The code works as I expected it to be, but I would like some feedback on the code itself ...
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3
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1
answer
155
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SystemVerilog: LED blinker control logic
I built this simple blinker in SystemVerilog and would very much like some help to make it better:
control.sv
...
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4
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1
answer
110
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I2C master interacting with ADC IC
The code is for an I2C master that interacts with an ADC IC (ADS1115).
Is there a more practical way of seeing what the internal regs and wires are doing in testbench, without creating a ports for ...
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4
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1
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273
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I2C serial communication protocol for university project
For now, I have only implemented a simple I2C protocol where only the master transmits the data. Also there is ack_bit for the I2C Address only. For state 5, i.e.,...
7
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1
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RISCV ALU Implementation in SystemVerilog
This will be first of many things I will submit during my journey of self (re)learning CPU design.
I have ALU implementation for RiscV base instruction. I am not fully sure what I am looking
for, but ...
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3
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1
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Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog
Question
How can I improve my Verilog code?
Context
Flash Read ID Operation
This project is an implimentation of the Read Manufacturer and Device ID (9Fh) operation ...
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3
votes
1
answer
121
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SPI prototype in Verilog: areas for code improvement
I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
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2
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1
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126
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Sensored BLDC commutation controller testbench code
This is testbench code for a combinational logic circuit with 6 input variables and 6 output variables. The 3 binary HS (hall sensor) input variables are signals given by the BLDC motors' sensors that ...
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3
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1
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Sensored BLDC Commutation Controller code
For context, I'm using a maxII epm240 cpld, and I want to be able to program this to FPGAs too. I know I could build this in a typical state machine fashion since a sensored BLDC motor controller is a ...
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3
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1
answer
106
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Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
4
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1
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162
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Design and stimulus for a simple Mealy finite state machine
I am trying to code a state machine for the given state diagram:
I
...
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2
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1
answer
262
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ROM memory in SystemVerilog and cocotb
The Verilog module describes a ROM memory. An initialization file is needed for the INIT_FILE parameter.
Below are Makefile, gtkwave.tcl to launch gtkwave, ...
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1
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1
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140
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Clock frequency meter module
The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
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2
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1
answer
320
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SystemVerilog implementation of an N-bit prefix adder logic design
I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
4
votes
2
answers
666
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Simple GPIO design module in SystemVerilog
I am designing a very crude general-purpose input/output (GPIO) module to provide IO pin control to a RISC-V (like) architecture microprocessor I am currently playing with.
This is the code so far:
<...
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2
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1
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93
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Variable output stream delay no shift register
I'm looking to improve my Verilog coding form by reducing utilization and learning any tricks more experienced Verilogers may know.
This module takes in a pulse data stream with pulses occurring ...
5
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1
answer
744
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LED matrix controller - Verilog
I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
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1
vote
1
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194
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fixed pseudo-random binary sequence (prbs)
On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
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4
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1
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375
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Heart beat RTL module
Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
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2
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1
answer
2k
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pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
- 453
3
votes
1
answer
2k
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Carry Lookahead Adder - SystemVerilog
I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
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2
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Generate a sine wave
This ip core simply generates a sine wave according a .mem file. It is required to specify rom depth equal to number of the sine points, the init file and the data size contained in the file. The ...
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3
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1
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3k
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Finding the carry out of the "+" operator in SystemVerilog
I'm trying to learn digital design this summer and currently going through this excercise of creating a 32-bit ALU based on this schematic:
Im using the + operator ...
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4
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1
answer
420
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A byte endian swapper
There are both a simple byte endian (little and big) order swapper and its testbench. A data stream inputs to the module and is converted to the other endianness by computational logic.
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3
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1
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129
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Pulse-width modulation module
Module for generating a PWM signal. The req_value_i input gets a duration value of the signal. Furthermore, the module can be stopped by deassertion of the enable_i input.
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2
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1
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AXI stream data generator
A Stream Data Generator which can take data from both a file or just a counter. This is needed for me as a testbench component for interfaces which works on one hand as an AXIS slave and on the other ...
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3
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1
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644
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Parameterized Verilog shift register code
I am a beginner in FPGAs, and I am studying Verilog HDL. Could you please check the quality of my code (a shift register)? Any comments are welcome.
The shift register serializes parallel from ...
- 453
3
votes
1
answer
903
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Range checking function
Here is the problem: Verilog code and testbench for detecting the range of the input given number. If input number is between 12 to 49 then output is '1' else '0'. Range should be easily programmable.
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2
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1
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310
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3-way multiplexer built on 2-way multiplexers in Verilog
I created this project on EDA Playground that builds a variable-width 3-way multiplexer out of 2 variable-width 2-way multiplexers. It will be part of homework that I assign, so I want to follow all ...
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6
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1
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342
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Full Adder in Verilog
I'll be teaching Computer Architecture at the undergraduate level this fall and want to make sure that my example Verilog code follows best practices. I welcome any suggestions, however minor, for ...
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6
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1
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844
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VGA sync generator for 640x480@60Hz
I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
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Verilog implementation of trapezoidal integration method
Any and all comments are welcome in this review.
##Problem
I've been doing a lot with numerical integration methods recently and have mostly been programming in Python. But, speedups and FPGAs are ...
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6
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2
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2k
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Simple SystemVerilog AXI controller
I have a more long-term project I'm using to learn FPGA/HDL, and this is first sub-component of it used for testing. I'm targeting Zynq device.
I'd like to create a component which creates an image. ...
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8
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2
answers
8k
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8-bit ALU in Verilog
I'm an EE student who's taken a a couple digital logic/design courses, but they were focused on schematic representation, so I'm teaching myself Verilog to implement what I've learned.
For a basic &...
3
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2
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8k
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4
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1
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413
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Haskell Parsec parser of Verilog-style number literals
I've set myself the task to write a function that parses Verilog-style number literals. In Verilog, numbers are written like this:
8'b10101100, ...
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7
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3
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4k
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Divide a clock signal by 8
I'm a new Verilog/HDL programmer, and I'm writing this post to get some feedback from more experienced programmers.
My very first task was to divide a clock by eight.
I know there are some better ...
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9
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2
answers
7k
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Verilog UART Transmitter
This is one of the first Verilog programs I have written. I have a Xilinx Artix-7 FPGA card. Right now I just have it transmitting an "X" every second. It works, and I can see the result ...
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28
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2
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3k
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4-stage pipelined RV32I CPU in Verilog
This is a simple 4-stage pipeline that partially implements the RV32I ISA.
All instructions are supported, except jalr, those relating to memory (...
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10
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2
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3k
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ALU design for a 16-bit microprocessor
I'm having a hard time figuring out if the code I wrote is purely combinatorial or sequential logic. I'm designing a simple 16-bit microprocessor (will be implemented on a Spartan 6), and I'm new to ...
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9
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2
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382
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Implementation of interface within state machine
This particular example is Verilog, but my question is more about the state machine structuring, which would be relevant to both VHDL and Verilog.
So if I have a state machine, this one is fairly ...
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