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About the AMDGPU category
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4
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703
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January 10, 2022
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How to Generate AMDGPU Code from MLIR? Is There a Pipeline Similar to -gpu-lower-to-nvvm-pipeline?
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3
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106
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October 19, 2025
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How to insert waitcnt to boost performance
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1
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92
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April 22, 2025
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TLS support in GPU progamming
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9
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211
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January 30, 2025
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Divergent Control Flow
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23
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692
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January 20, 2025
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Exploring LLVM's Role in FPS and Power Consumption Optimizations for GPUs
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3
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204
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October 28, 2024
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How to verify correct regalloc for a kernel?
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5
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250
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August 24, 2024
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some dialects in AMGGPU dialects are equal to ROCDL dialects , Is it redundant?
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1
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156
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June 20, 2024
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Mysterious assembler documentation in llvm/docs/AMDGPU
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3
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242
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March 8, 2024
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Investigating high register pressure (at the IR level?)
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2
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504
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April 11, 2023
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Representing buffer descriptors in the AMDGPU target - call for suggestions
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65
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2648
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April 4, 2023
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Handling multiple exits in StructurizeCFG
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2
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314
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March 9, 2023
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Handling PHIs in Uniformity Analysis
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3
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486
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February 23, 2023
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[AMDGPU][LLC][LLVM] Cannot select: intrinsic %llvm.amdgcn.if
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0
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589
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February 14, 2023
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Catching up on uniformity analysis
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5
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508
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February 13, 2023
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Convert NVIDIA GPU LLVM IR(NVVM) alloca instruction to AMDGPU's
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7
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1261
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September 9, 2022
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[AMDGPU] Drop the GCNRegBankReassign pass
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1
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434
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January 17, 2022
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GCNRegBankReassign pass issue
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0
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462
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January 11, 2022
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The current state of spilling, function calls and related problems
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0
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1969
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February 19, 2021
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