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About the Code Generation category
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4
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844
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January 11, 2022
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[RFC] Adding SFrame support to llvm
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60
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3799
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December 12, 2025
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Extending llvm_jump_table_sizes
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8
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486
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December 11, 2025
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How to force two virtual register allocate to the same physical register in LLVM?
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1
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51
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December 8, 2025
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Fast register allocation - ran out of registers
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8
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226
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December 5, 2025
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Running out of bits in TSFlags
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3
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121
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December 4, 2025
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Optimizing Load-multiple and Store-multiple on LLVM
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0
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46
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December 4, 2025
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RISC-V LLVM sync-up call December 4th 2025
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0
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24
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December 3, 2025
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Questions about best approach for upstreaming CUDA i128 support
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11
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287
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December 3, 2025
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LLVM backed for handling UMUL8 and UMUL16 for PSIMD RISC-v
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0
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25
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December 2, 2025
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RISC-V LLVM sync-up call November 20th 2025
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0
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38
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November 19, 2025
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SiFive P550 nightly performance tracking on cc-perf.igalia.com
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3
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164
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November 17, 2025
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[RFC][DwarfDebug] Fix and improve handling imported entities, types and static local in subprogram and lexical block scopes
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12
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1165
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November 13, 2025
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Garbage collector examples wanted
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2
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172
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November 13, 2025
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GlobalISel sync up - Nov 11 2025
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3
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143
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November 11, 2025
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[TableGen] How pattern should look like for multiple output node?
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2
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81
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November 11, 2025
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Memory Prefetching Support in LLVM
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12
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1490
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November 10, 2025
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[MC] How/why does converting "relocation against symbol" to "relocation against section" work?
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6
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118
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November 7, 2025
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RISC-V LLVM sync-up call November 6th 2025
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0
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47
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November 5, 2025
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Spill/fill for sub-registers
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1
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131
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November 4, 2025
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MCExpr::print add support for more targtes
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2
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77
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November 3, 2025
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Is a Segment Tree based Register Allocator worth pursuing as an LLVM contribution?
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4
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284
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October 27, 2025
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Encoding of explicit parallel instructions
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4
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140
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October 27, 2025
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RFC: Lower memcpy into sve load/stores when the memcpy size is statically unknown but mostly small
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1
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121
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October 24, 2025
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RISC-V LLVM sync-up call October 23rd 2025
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0
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41
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October 22, 2025
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Lib call selection
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2
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67
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October 21, 2025
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[RFC] Out of LaneBitMask Bits Again
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6
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292
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October 20, 2025
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How to Generate AMDGPU Code from MLIR? Is There a Pipeline Similar to -gpu-lower-to-nvvm-pipeline?
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3
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106
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October 19, 2025
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[AVR] register allocation issue - help/advice with debugging
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12
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221
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October 17, 2025
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RFC: Generic DAG nodes for floating-point operations
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5
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191
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October 17, 2025
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