4,641 questions
1
vote
1
answer
39
views
ifdef with target-specific variables
This Makefile specifies a target-specific variable and a global one
VAR=value
target: VAR2=value2
ifdef VAR
VAR3+=$(VAR)
endif
ifdef VAR2
VAR3+=$(VAR2)
endif
target:
@echo $(VAR) $(VAR2)...
- 709
2
votes
1
answer
47
views
Gnu make 4.3 Makefile change output directory of dynamic target
I am trying to compile .c-files and store the output .o-files into different folders. When making a debug-build, the output files should be stored in build/debug/. When making a release-build, the ...
- 61
Advice
5
votes
0
replies
111
views
optional prerequisites in gnu make
I have a project where I need to build a series of targets. If the target has a same-named 'suppsrc' file that can be transformed to a 'supplement' file, use that too.
That is, if I have a file a.in, ...
- 217
0
votes
1
answer
77
views
Why doesn't make fail if a file exists but there is no rule for it
The following is a minimal example from something odd that was happening to me. My situation was obviously more complex than what follows, but the "misunderstanding" boils down exactly to ...
- 299
0
votes
2
answers
68
views
How to apply the same recipe to different target with pattern?
Here is my Makefile. All the %.o depend on %.c and main.h, except the ones under main, event, cmd folder, which depend on $(MAIN_HEADERS).
How do I combine the below and make them simpler, as their ...
- 149
-1
votes
0
answers
30
views
multiple targets in Makefile [duplicate]
I have a very simple Makefile:
a b c:
@echo work done for target $@
I would expect, that the echo command is run for any of the 3 targets. I would expect the output:
work done for target a
work ...
- 1
0
votes
1
answer
43
views
Why does my recursive Makefile target exit with ‘is up to date’ and no error, unless I redeclare all
I have a recursive Makefile setup where a root Makefile delegates builds to subdirectory Makefiles via $(MAKE) BUILDTARGET=.... Most subdirectories build fine, but the boot/ directory behaves ...
0
votes
1
answer
93
views
Makefile not building pattern rule prerequisites when it involves a chain [closed]
Consider this Makefile:
run-%: %
./$<
I have a test1.cpp file, so I expect make to build test1.o and test1 using chained implicit rules when I run make run-test1. However, what I get is
make: *...
- 386
-4
votes
1
answer
61
views
I want `make` to fail if an environment var is not specified
I want GNU make command to fail if the environment var AUTO_CALL is not specified.
I could do so:
.PHONY: x
x:
ifndef AUTO_CALL
@echo "Don't call `make` manually."
else
...
endif
...
- 5,909
2
votes
1
answer
56
views
GHC(Haskell) not picking up imports from makefile
I have been making a Haskell project that I want to continue on in C at some point through the FFI. I wanted to create a makefile to compile all the source with Clang for C and GHC for Haskell.
The ...
- 53
1
vote
0
answers
75
views
Usage of sed in Windows OS via Make
I am working on Windows OS. And here is my makefile snippet.
COMPILER_ROOT := C:/Users/kpt
DATE := $(COMPILER_ROOT)/build/busybox_glob.exe date
SED := $(COMPILER_ROOT)/build/busybox_glob.exe sed
...
- 45
1
vote
2
answers
59
views
gnu make executes commented $(info ) within define
I cannot comment out an info line inside a define. The following makefile shows the behavior (mind the tabs)
define tmpl
$(info info inside define, not commented, parameter is: $(1))
# $(info info ...
- 3,791
0
votes
0
answers
32
views
gcc-15.1.0 installation error on TinyCore64 Linux
While installing GCC-15.1.0 on
TinyCore64 Linux on
Oracle VirtualBox on
Windows 11 Home
on Acer Aspire Thin & Light Laptop with AMD Ryzen 5 5625U with 48GB (16GB+32GB) RAM & 512GB NMVe gen3.0
...
- 1
1
vote
1
answer
83
views
How to use shell-assignment operator with gmake?
I'm trying to keep my Makefile compatible between BSD and GNU make. It is not particularly complicated, but there is one spot, where I'd very much like to assign a value based on the output of a ...
- 4,266
3
votes
1
answer
215
views
Using GNU Make to compile all .c files in a subdirectory
I'm working on a project in C, and I'm using GNU Make to handle compiling everything, but I'm having a lot of trouble trying to compile every .c file in my project, including ones in subdirectories. ...
- 45
0
votes
0
answers
36
views
Need a little help using the system move command in a makefile
I have a makefile that has to deal with building for both Windows and Linux platforms. I use wsl for the Linux testing. I have a build tree as thus:
makefile
src (sub makefile in here as well)
obj
man
...
0
votes
1
answer
43
views
What does :| mean in g++ generated .d file
I encountered the following line in a g++ generated .d file
"/home/test/file27.gcm":| /home/test/file27.o
What does ':|' means compared to ':'
I could not find any mention of it in gnu make ...
- 63
0
votes
2
answers
77
views
GNU Make variable values with special characters
I have an issue in a Makefile where I'm trying to read a value in from an AWS secret manager secret into a Make variable as follows:
$(eval SECRET_NAME := some/aws/secretname)
$(eval SECRET_FILE := ....
- 1,310
0
votes
0
answers
42
views
String comparison in a makefile: incorrect result
In a makefile I need to check, whether a program rocq exists in the system. If it exists assign one value to the variable, otherwise assign another value.
I created the following code:
OUTPUT=$(shell ...
- 24k
2
votes
2
answers
94
views
How can I override a C header residing in the same directory as the source which includes it using only the make call?
The project I am working on is required to incorporate sources from a previous project, however, the configuration of that code differs between the legacy and current project. The legacy source uses a ...
- 709
0
votes
1
answer
31
views
GNU Make error when trying to determine the elapse time of a target
I am trying to setup each target to measure the elapse time the target takes when using a GNU Make file. I started to prototype this code.
date:
start_time := $(date +"%S")
@echo "Start ...
- 31
0
votes
1
answer
137
views
how to create macros in makefile to insert the symbols not available in one variable
In a makefile, I want to have a macro that inserts some symbols/source code from one variable into another one if those symbols/source code do not exist in the destination variable:
the way I want to ...
- 13
1
vote
0
answers
48
views
single prerequisite for multiple targets
I would like to have a single list of prerequisites to be used in multiple targets. I came up with the syntax below. For some reason I have to have the string substitution rules both in the assignment ...
- 328
1
vote
1
answer
51
views
Using foreach in Makefile to compile subdirectories separately
I have the following Makefile sample:
BUILD = build
PATH_POT3 = src/pot/pot3/
MPIFC = mpiifort
FFLAGS = -O3
MOL_LIST = $(shell find $(PATH_POT3) -mindepth 1 -maxdepth 1 -type d)
$(foreach MOL,$(...
- 203
0
votes
0
answers
100
views
Kati says rule for target is being overwritten even though that target isn't installed in Android build
I'm compiling a custom build of AOSP 12.1 r27 with my own device tree.
I've added the following line to device.mk
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/prebuilt/[email protected]:$...
- 181
2
votes
1
answer
103
views
Linker cannot find references to defined functions between automatically generated objects in Makefile
I ran into a problem when the linker complains about undefined reference to <function> after compiling all the objects and files, even though functions are declared and defined. I've been ...
- 41
0
votes
1
answer
182
views
Build or use astrometry.net natively on Windows 11
I would like to use the astrometry.net software suite on windows, specifically the executable files, not the web interface.
However, there are no recent and maintained binaries for Windows I could ...
- 3,347
0
votes
0
answers
55
views
autoconf does not generate shared object
I inherited a fairly large project, built with autoconf. It builds fine in static, but has a very strange behavior when building shared, namely the libfoo.so is created as a symbolic link to libfoo.so....
- 17.9k
2
votes
2
answers
82
views
Gnu makefile looping through list, first item is empty and last item is skipped
I have a makefile with a loop that should iterate through the elements in a list and pass each element to a function. In the first iteration, it seems to pass a blank element, and then it never passes ...
- 33
0
votes
1
answer
45
views
Why does this recipe run for a second time even though there are no changes in its dependencies?
Please consider the following setup:
$ ls
base.mk file.ext Makefile
$ cat Makefile
include base.mk
algorithm = another-alg
$ cat base.mk
source = file.ext
binary = $(algorithm)
algorithm = the-alg
...
- 845
1
vote
2
answers
76
views
How can I define a dependency in Make if all files reside in different folders but with similar structure (language dependent)?
I want to use the tool msgfmt in a makefile to generate .mo files from .po sources. The .po sources are per language and reside in a folder structure like this:
$(projectpath)/locale/de/LC_MESSAGES
$(...
- 174
1
vote
2
answers
94
views
Makefile: How does a header file change trigger a target?
I have the below Makefile.
#
# General Makefile
#
BUILD := build
CXXFLAG := -std=c++20
CXX := g++
SRC := 16.15.cc
OBJ := $(SRC:%.cc=$(BUILD)/%.o)
DEP := $(OBJ:.o=.d)
MKDIR_P := mkdir -p
all: ...
- 3,811
3
votes
1
answer
99
views
How to refactor repetition inside a Makefile?
Here is a Makefile I made, it is quite explicit but also maybe too verbose and I wonder if it would be possible to change things (whether it be the logic or the directory structure itself) in order to ...
- 98
0
votes
1
answer
77
views
Pattern Rule: Filtering Prerequisites with Targets & Prerequisites in Different Directories
The following Makefile
configs = $(filter-out $(wildcard ./configs/project/*/root.yaml), $(wildcard ./configs/project/*/*.yaml))
.PHONY: compile
compile: $(configs:.yaml=.sql)
%.sql: %.yaml
@...
- 4,211
4
votes
1
answer
345
views
Automatic GNU make with C++20 module
In the last few weeks, I've been experimenting for the first time with C++20 modules after reading about them for years. I extensively worked with them in Visual Studio and I did some successful test ...
- 1,088
0
votes
1
answer
266
views
Make: forked process died unexpectedly, exit code 0xC0000142 (Error 127)
During R package installation on Windows, make fails on the step of detecting gcc:
> devtools::install('c:/Temp/REddyProc-1.3.3')
── R CMD build ─────────────────────────────────────────────
✔ ...
- 1,055
1
vote
1
answer
68
views
How to unconditionnally re-assign a variable in a makefile (with submakefile)?
I am trying to re-assign a makefile variable (depending on its initial value), while keeping the new value in a submakefile.
Here is the layout:
Makefile
subdir/
- Makefile-sub
Main makefile:
...
- 69
0
votes
1
answer
113
views
Installing solver library with MSYS2 - HSL compiling and linking
I am trying to install Coin-HSL (https://licences.stfc.ac.uk/product/coin-hsl) to use with CasADi in Matlab on Windows.
I did the following:
Install MSYS2 in C:/msys64
In MSYS2 I installed the ...
- 11
0
votes
0
answers
89
views
Compile gmake with TCC in musl libc system
I'm trying to compile gmake with tcc in a (gentoo) musl-libc system. I first configure with CC=tcc ./configure --program-prefix=g then ./build.sh but I get the following error:
config.status: creating ...
- 11
2
votes
1
answer
33
views
Parallel processing of variable argument list
I have a makefile that is running a custom program on large numbers of input file. The program has large startup cost, and is more efficient processing multiple files in the same run
I would like to ...
- 14.7k
-1
votes
1
answer
36
views
Pair source and target in Make rule
It's been a very long time since I had to use Make, and I remember there was a trick to do this, but my memory fails me, and the vocabulary is too general for the search...
So:
SOURCES := $(wildcard */...
- 9,713
0
votes
0
answers
82
views
Makefile shell function call is causing recursion?
I want the result of the tool in REVTOOL and its parameters returned into variable REV. I tried with this call in my makefile:
commonbase := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
...
- 507
0
votes
1
answer
38
views
gmake: command must run that MIGHT regenerate a .cpp file in a VPATH
I have a command that will check foo.cpp and MAY regenerate it. Regeneration is based of factors that aren't knowable to make, so I must run the command every time.
libfoo.a depends on foo.o which ...
- 2,514
1
vote
1
answer
43
views
What does this do in make?
I've been reading the make manual to try to decypher an existing Makefile. I'm stuck on the filter-out in this line:
KERNEL_ELF_DEPS = $(filter-out %: ,$(file < $(KERNEL_ELF).d)) $(KERNEL_MANIFEST)...
- 618
0
votes
1
answer
45
views
gmake-ing a Makefile, if one doesn't exist, in child directories before switching there to recursively make
I want my gmake to recursively gmake in all subdirectories, but first copy a Makefile to a given subdirectory before running make there, if it doesn't already exist.
The following works perfectly, but ...
- 2,514
0
votes
0
answers
74
views
Why does = fail to concatenate variables in GNU Make on WSL, but works fine with :=?
Body:
I am experiencing a strange issue with GNU Make on WSL (Windows Subsystem for Linux). When using = for variable assignment, concatenation doesn't work as expected. However, when I switch to :=, ...
- 1
0
votes
0
answers
40
views
Unable to compile Apache TVM runtime for MIPS platform
I am trying to build Apache TVM library for MIPs platform using steps explained on this page for RISC.
Following are the steps I followed:
$ sudo apt-get update
$ sudo apt-get install g++-9-multilib-...
- 3,029
0
votes
2
answers
57
views
2 patterns in Makefile target
This makefile can generate images for each page of PDF documents:
%.pdf:
wget http:/example.com/$@
doc_0-page_0.png: doc_0.pdf
convert "$^[0]" $@
doc_0-page_1.png: doc_0.pdf
convert &...
- 55
1
vote
1
answer
43
views
No recipe in automatically generated dependency files
I've generated dependency files (*.d) automatically with make (using g++ -MMD), and in these files I see that the rules created don't have any recipes. Moreover, from my testing, I've noticed that ...
- 3,457
0
votes
2
answers
55
views
Conditionally updating a target in a Makefile
I have a tool that I use to generate C++ header files as part of the build. I only want to write out the generated headers if they changed from what is already on disk so that I don't trigger a ...
- 1