1,424 questions
2
votes
0
answers
83
views
Devtool with/without running bitbake first
I don't understand how to use devtool properly for my Yocto project. I started using it in order to patch the kernel as suggested by the Yocto Project. I just don't understand why it behaves ...
- 31
0
votes
0
answers
107
views
Vivado Block Memory Generator IP not accepting COE file
Here is my python script to generate a COE file:
import numpy as np
def generate_coe_file(filename, data_list, radix=16):
with open(filename, 'w') as f:
f.write(f"...
0
votes
0
answers
68
views
Xilinx Zynq 7000 pin number under Linux
If I'm working for example with the Xilinx ZU2CG SoC, and a pin named as an "AC3" (xczu2cgsfvc784 pinout) is interesting for me, where can I find what is the gpio number under Linux for that ...
- 105
0
votes
1
answer
61
views
`$display` cannot display right value in vivado
`timescale 1ns / 1ps
module factorial(
input i_n,
output reg res,
input i_clk
);
integer j;
initial
begin:a
for (j=1;j<=i_n;j=j+1)begin
res<=res*j;
end
res<='d3;
$display("res is ...
- 2,511
-1
votes
1
answer
266
views
How to set up handler for microblaze interrupt?
I'm trying to use microblaze interrupt to handle with simple gpio button interrupt. In the block, only gpio and uart is used as well as interrupt controller. Interrupt controller is set for level ...
- 11
3
votes
1
answer
371
views
Mixing C and C++ in Vitis
I need to mix C and C++ code in Vitis. I use C specific syntax in my C code that is not supported by the C++ compiler (specifically array initialization with explicit indices). This means I get an ...
- 195
0
votes
0
answers
125
views
How to simulate a Xilinx IP using Cocotb makefile?
I have a VHDL design that includes the Xilinx FFT IP, and I am using cocotb with Aldec Riviera for the simulation.
In the cocotb makefile, I insert all my vhdl source files (including the .vhd file of ...
- 81
-1
votes
1
answer
184
views
How to use `get_nets` to find `wire` in Vivado when get Vivado 12-1023 warning?
Verilog script as below:
`timescale 1ns/1ps
module Save_Mult_Df(A);
input A;
wire C;
assign C=A;
endmodule
module test();
reg A;
wire C;//should wire be added to testbench?
initial
A= 2'b10;
...
- 2,511
0
votes
1
answer
93
views
For some reason, when allocating memory from user space linux, I have a problem with the write response in AXE Memory Mapped to PCI Express module
I have a PC as a root complex and Xilinx fpga device as an end point that writes via PCI Express to root complex RAM using DMA and a linux driver to it. I have a problem that I can't solve in any way. ...
- 1
0
votes
0
answers
55
views
m_axis_result_tvalid is not asserting during floating point operation
I'm trying to do some operations in a Xilinx FPGA. Here is my code. When i simulate the code, the error validation signal does not assert. i need the signal to allow the next step of operations to ...
- 11
0
votes
1
answer
1k
views
Vivado 2024.1 – Warning: [Synth 8-7080] Parallel synthesis criteria is not met – what does it mean and how to resolve it?
I'm using Vivado 2024.1 with full-project synthesis (not out-of-context), and I’m getting this warning during synthesis:
[Synth 8-7080] Parallel synthesis criteria is not met
The design builds and ...
- 6,769
0
votes
0
answers
55
views
Why HLS C++ code generates non specified input?
I'm learning the basics of High-Level Synthesis (HLS) using AMD/Xilinx tools. Most courses use older tools for the practical examples (Vivado HLS instead of Vitis 2024.2 which I'm using).
This is the ...
0
votes
0
answers
54
views
Access DDR using petalinux, what is the most prominent solution
Im using xilinx which runs on petalinux, I want to access a DDR and fetch the values from DDR and print that using petalinux. Im confused on how to do that, since I'm very new to this. Can anyone ...
- 1
0
votes
0
answers
51
views
I am trying to use my custom library linking to R5 core application but it is giving error and ELF is not created
The error is I am getting when I build the application in vitis IDE is as follows:
make all
'Building file: ../src/prhp_rpu_0_module.c'
'Invoking: ARM R5 gcc compiler'
armr5-none-eabi-gcc -DARMR5 -...
- 1
1
vote
1
answer
70
views
Xilinx 7 overwrite LUT contents after flashing
I want to be able to change device behavior during work
Can I overwrite INIT values of LUT within FPGA work process?
I've seen, that I can use it as LUTRAM, but I also want to be able to shift data ...
- 181
1
vote
1
answer
111
views
Why does my Mealy FSM written in VHDL get stuck in the wrong state at the end?
I'm making a beverage vending machine with the inputs: clk, reset, leu1(1 of currency), lei5(5 of currency), 10lei(10 of currency), 3 product inputs: product_3lei(costs 3 of currency), product_5lei(...
0
votes
1
answer
65
views
NEC Infrared Transmission Protocol in C lanc on Xilinx [closed]
I need to capture and decode an infrared signal (with NEC infrared protocol) using a GPIO pin on a Xilinx FPGA and show the content of the signal on the console. I receive the signal on the address
...
- 63
0
votes
1
answer
157
views
How to solve "Multiple init scripts found (meta-openembedded vs. poky). Resolve ambiguity by removing one of the repos" without removing one repo
There is another very similar question here but it has no answer so ill try anyway
Im using Kas 4.5 to setup a yocto build
I need meta-xilinx which requires openembedded meta layers
https://layers....
2
votes
1
answer
331
views
Armv7 MMU on the ZYNQ-7000 not starting the virtualization
Introduction
I have been trying to evaluate the MMU functionality for the Xilinx zynq7000 soc that contains 2 A9-Cortex processors.
Firstly I have tried using the xil_mmu.h library, however after ...
- 71
1
vote
1
answer
80
views
Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
I am using Vivado 2023.1, and I am not able to connect the output of the RTL module to the AXI GPIO output that is connected to the LED. Please take a look at the attachment. RTL is below
module ...
- 469
-1
votes
1
answer
820
views
how to force block ram instead of LUT in VHDL?
xc7s25csga225-1 FPGA
Vivado v2023.2.2 (64-bit)
VHDL
i keep getting the error:
[DRC UTLZ-1] Resource utilization: F7 Muxes over-utilized in Top Level Design (This design requires more F7 Muxes cells ...
1
vote
1
answer
335
views
Ambigious clock in event control
I want to generate a slow clock from input clock which is clk_in, but it shows the following error:
ambigious clock in event control
module clk_div_h(rst, clk_in, clk_div);
input rst, clk_in;
...
- 11
0
votes
1
answer
79
views
How should task be used?
I decided to use verilog task feature to write generic and readable code and I'm having trouble with it.
When I write and call it with Task, it does not see the outputs of the circuit, it only writes ...
- 1
0
votes
1
answer
158
views
How do I get the directories of the IP-cores of the Vivado project?
There is a get_ips function, it returns a list of names of all IP-cores of the project. Is there any way to get the directories where the files of these IP-cores are located by some function?
-2
votes
1
answer
430
views
How to handle the read latency in Async FIFO?
I am using Xilinx FIFO generator core in my project. I have module, say M1, which assersts fifo_rd_en signal to the fifo that i am using. However, the fifo has a read latency of 2 clock cycles. How ...
0
votes
1
answer
1k
views
How to simulate Xilinx IP-cores in Modelsim?
I have Vivado 2016.4 and Modelsim 2021.3 installed. My Vivado project contains Xilinx ip-cores. I want to model everything in Modelsim. It is useless to choose the Modelsim simulator in the simulation ...
1
vote
1
answer
123
views
Is CRC Calculation Faster on Xilinx Alveo U280 FPGA Using a Custom Algorithm or a Lookup Table?
I am working on a project where I need to implement CRC (Cyclic Redundancy Check) on a Xilinx Alveo U280 FPGA. I am considering two approaches for CRC calculation and would like to understand which ...
- 256
1
vote
1
answer
85
views
4-bit counter that increments after every second: simulation always shows xxxx at the output
Here's my code:
//`timescale 1ns / 1ps
module FourBitLedToggle(
input res,
input Clk,
output [3:0] led
);
reg [27:0] count;//for 1 second check
reg clk1s;//1 second clock
...
0
votes
1
answer
331
views
How to implement pipelined floating point accumulation in II=1 in Vitis/Vivado HLS?
I'm trying to implement a pipeline in Vivado HLS with an initiation interval (II) of 1 for a floating-point accumulation loop, but I'm encountering an II violation(Resource is not my concern, I really ...
- 383
0
votes
1
answer
242
views
Timing simulation in Vivado giving an error
I am trying to implement and simulate ring oscillators in Xilinx Vivado with the LUT6 primitive. When running the Behavioral Simulation it runs fine, and I can see the signal switch every 5 ns due to ...
- 13
0
votes
1
answer
248
views
How to combine a FSM with BRAM?
My project is as follows: I want to save the pixel values coming via UART to BRAM first, then pass them through an image processing filter, and send them back via UART. Currently, I want this filter ...
- 1
0
votes
1
answer
180
views
Is it possible to tie ports high always high outside of top module?
I'm programming the Xilinx BASYS 3, Artix 7 board. It has 7-seg display with 4 anode ports. When I ignore them in code they are low causing the 7-seg to be on. Is there a way to make tie them high in ...
- 73
0
votes
1
answer
140
views
Verilog code getting X for the signals in the simulation
I am new to verilog and I have two Verilog modules and a main.v module that is a topmodule and I want to simulate it with vivado xilinx. This is my main module. When I try to simulate it, I get X ...
- 45
0
votes
1
answer
84
views
Undefined ALU result value (VHDL)
Im working on this VHDL 16 bit MIPS processor, and im encountering some problems with the Execution Unit, more specifically the ALU Result. I've created a test bench individually for the ALU (which ...
0
votes
0
answers
37
views
Substitution to DirectFB Library
I am struggling on a Linux application (On a Xilinx Zynq Ultrascale ). I try to use as CPU based app without GPU for drawing. I am trying to draw a rotating rectangle with a texture inside with the ...
- 1
0
votes
1
answer
201
views
Can SYSCLK be included in FPGA Xilinx vivado testbenches?
I'm doing a fairly simple design. I have the VC707 FPGA Evaluation Board and from the SYSCLK(P/N) I'm generating a single-ended clock for the rest of the board.
// Differential to single ended buffer ...
- 25
0
votes
1
answer
176
views
Are FPGA GPIOs capable enough to read bits at a high rate (26Mbps)? If not, what is a possible way? [closed]
I had two systems, let's say, system A and system B, so system A generates bits at the rate of 26Mbps from a physical pin, I need to capture/read all the data with system B which is ZC706 FPGA/any ...
1
vote
0
answers
284
views
embedded linux buildroot how to work with axi-gpio?
I'm learning embedded linux on Zedboard using buildroot, so I'm relatively new to this. I don't understand how I can configure and interact with axi-gpio IPs from PS in the userspace. I already ...
- 11
1
vote
2
answers
157
views
how to implement a Vhdl code for 2bit karatsuba algorithm
I am trying to write a VHDL code on Karatsuba algorithm but facing errors in the following code regarding operator + cannot determine exact overloaded matching.
library IEEE;
use IEEE.STD_LOGIC_1164....
1
vote
1
answer
655
views
Timing closure problems in FIFO
I have a FIFO implementation in Verilog that is based on this article: CummingsSNUG2002SJ_FIFO
Whilst using this FIFO as a CDC FIFO, with the read side being clocked at 100Mhz and the write side at ...
- 71
1
vote
2
answers
670
views
Xilinx Vivado schematic for if else statements
I am learning SystemVerilog. While coding, the synthesis schematic for the following if statements don't make sense to me.
module ifelseDUT(
input logic sela, selb, selc, da,db,dc,
output logic dout
...
- 131
0
votes
1
answer
339
views
Isim not running
I'm trying to run a full adder testbench. When i try to run the isim simulator it says "Running: Convert Schematics to HDL" then "No process Running". It doesn't even open the isim ...
- 147
0
votes
1
answer
221
views
How to enable PMU GIC Proxy on Xilinx ZCU102?
My board is Xilinx ZCU102, and I need the GIC Proxy functionality to achieve UART interrupt. Here is my configuration.
According to the official documentation, to activate the PMU's GIC Proxy, the ...
- 63
1
vote
0
answers
474
views
How to trigger a software generated interrupt on core1 from core1 on bare metal?
I'm trying to trigger a software generated interrupt on core1 from core0 on the Zynq Ultrascale+ Platform. Sadly however no interrupt ever reaches core1.
I tried multiple approaches also using the ...
- 1
1
vote
1
answer
2k
views
difference between Xilinx solarflare scaleout onlod, solarflare onload, and solarflare TCPDirect?
According to this picture,
there are five different types of solarflare TCP methods.
First and the last types are not really important because i am aware of them
but i do not know the difference ...
- 41
0
votes
0
answers
362
views
xilinx uartps interrupt headler is not working (Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit)
My board is the Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit, and I need to port the UARTPS driver to run on the PMU. When I execute xuartps_intr_example.c, it hangs within the while loop at line 285. ...
- 63
-1
votes
1
answer
708
views
Type conversion issue with 'std_ulogic' - seeking guidance
I'm working on a VHDL project involving button presses, and I've encountered an issue that I can't seem to crack. In the following line of my code:
button_counts(i) <= std_logic_vector(unsigned(...
0
votes
0
answers
180
views
QDMA DPDK driver results "Packet Length Mismatch" Error during data transfer
I am new to DPDK and QDMA. I am using alveo u200 with OpenNIC. I have bind the interface with VFIO-PCI driver. While executing Pktgen/TestPMD Application I am getting "Packet Length mismatch ...
- 1
1
vote
1
answer
97
views
is it okay to assign 1 bit reg data type element to 4 bit reg element?
i am trying to implement a rtl code where i am giving 1 bit reg data type to an 4 bit reg data type under always block.
lets say X & Y are two reg data type.where X is 4 bit reg data type and Y ...
1
vote
1
answer
188
views
'case item is unreachable' in Vivado synthesis process
`timescale 1ns/1ps
module lcd_control (
input clk,
input reset,
input prod1,
input prod2,
input prod3,
input prod4,
input disp_up,
input disp_down,
input confirm,
...
- 15