3,630 questions
0
votes
1
answer
68
views
Connection using modports with different signals [closed]
Is it allowed to connect two modules using SV interface modports with different signals?
interface chip_bus ();
logic [31 :0] address;
logic [63:0] data;
logic [63:0] req;
// The two ...
- 45
2
votes
2
answers
95
views
Proper way of resetting a FSM
I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...
- 21
2
votes
1
answer
87
views
Not seeing one-cycle delay for register in Modelsim
My register doesn't work properly. The output changes simultaneously with the input. There should be a one-cycle delay, but I am not seeing it from the simulation in Modelsim. Does anyone know why?
...
- 61
2
votes
1
answer
89
views
Why is my simple ARM7 data memory on Verilog failing tests?
I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this:
// very simple sdata implementation with 1mb~ memory
...
- 301
1
vote
1
answer
123
views
Random stability with non-random object
I have a simple example for random stability in QuestaSim.
module sv_rand_stability;
class dummy;
rand int data;
endclass
initial begin
dummy d;
$display("%...
1
vote
1
answer
100
views
Is conditional bracket pairing possible?
In SystemVerilog is the "property" construct:
property <name>
<body>
endproperty
This can then be instantiated as:
assert property(<name>);
In the language extension ...
- 29
-1
votes
1
answer
95
views
What's point of port to port type of connection in TLM? [closed]
In UVM TLM1, there are three main interface types:
port — the initiator of a transaction,
export — a proxy that forwards port requests to an implementation,
imp — the implementation, which contains ...
0
votes
1
answer
64
views
System verilog constraint for queues with fixed number of 6s
Can someone help me with system verilog constraint for the below requirement.1) Fixed queue size of 10 and has four 6s in it at random position.
I tried the below constraint to start with.
class ...
- 11
-1
votes
1
answer
85
views
In a System Verilog FSM can a repetitive State be converted to a Task?
I'm writing an FPGA state machine in System Verilog to read bytes from a SPI port and parse them into commands to the FPGA. The "RXSPIBITS" state is used to read SPI bytes by multiple other ...
- 9
4
votes
1
answer
127
views
How can I simulate a simple elevator FSM where it can detect overweight?
I've been doing a finite state machine of an elevator using Verilog. The elevator contains four states:
IDLE: When the elevator is stopped.
ERROR: When the elevator's weight limit is exceeded.
MOVING:...
- 71
-1
votes
1
answer
109
views
How to swap inout wires within a contained hierarchy (of which is synthesizable)?
For context, please look at my attached diagram to see what I am trying to accomplish.
Essentially, I want to swap inout wires using a contained hierarchy that will allow me to have more modular RTL ...
- 181
2
votes
1
answer
82
views
Usage of assign: when to put it in an always or not [duplicate]
I know a lot of people have asked about when to use assign inside always, but I'm wondering if you actually have to. Is it ok to have a module where you have assign statements, but they are not inside ...
- 21
1
vote
1
answer
106
views
Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]
I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.
Should I develop my ...
- 139
2
votes
2
answers
174
views
In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?
When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows:
module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
always @(posedge clk or ...
- 77
0
votes
0
answers
71
views
Why does module instantiation affect output reg value in vivado? [duplicate]
The instantiation module as below:
module second_module(
input [7:0] d,
output reg [7:0] q
);
initial
q <= ~d;
endmodule
The top module as below:
module top_module(
input [7:0] ...
- 2,511
0
votes
1
answer
92
views
`$strobe` and `$display` output different result for the same target
Refer to this question,I write a similar case.
module n;
reg [1:0]a, b;
initial begin
a=1;
a<=a+1;
$strobe("strobe",a);
$display("display",a);
end
endmodule
The ...
- 2,511
1
vote
1
answer
80
views
Why `$monitor` output assignment result before time step?
module n;
reg [1:0]a, b;
initial begin
$monitor($time,," monitor ",a);
a=1;
a<=a+1;
#1;//assignment should happen here
end
endmodule
The expect output is:
1 monitor 2
but I got
0 ...
- 2,511
0
votes
1
answer
61
views
`$display` cannot display right value in vivado
`timescale 1ns / 1ps
module factorial(
input i_n,
output reg res,
input i_clk
);
integer j;
initial
begin:a
for (j=1;j<=i_n;j=j+1)begin
res<=res*j;
end
res<='d3;
$display("res is ...
- 2,511
-1
votes
1
answer
110
views
How to run iterations through a module instance without using generate in Verilog
I'm a complete beginner when it comes to Verilog.
I have a block ROM which is as follows:
module CDbram_2_0_32 (clk, en, addr, dout);
input clk;
input en;
input [9:0] addr;
output [9:0] dout [0:37];
(...
1
vote
2
answers
126
views
Confusion about nonblocking assignments to signals for synchronous logic
I have Verilog code like this:
module gen_bits(input clk, input clear, input ld, input in, output reg[7:0] out);
always @(posedge clk) begin
if (clear)
out <= 8'b00000000;
...
- 53
0
votes
0
answers
41
views
Switch Level Transmission Gated Master Latch testbench
I'm currently doing preliminary testing on a switch level transmission gate master latch. The design is adiabatic and is part of a flip flop circuit. The adiabatic operation is done through Bennett ...
-1
votes
1
answer
74
views
yosys - Get rid of `\` in synthesized module names
Consider the following example:
// example.v
module submod (
output logic sub_output
);
assign sub_output = 1'b1;
endmodule
module top;
logic out;
submod gen_submod ();
assign out ...
- 195
0
votes
1
answer
147
views
System Verilog Assertion to detect delta cycle glitch on signal
I am hoping to define an SVA property that detects a zero-time (delta cycle) glitch on a signal. I have found a recipe that I expected to work for high-going glitches, but it turns out it also works ...
- 940
1
vote
1
answer
96
views
System Verilog equivalent of VHDL's "wait until rising_edge() for ..." followed by "if rising_edge()"
I'm looking for SV code that is equivalent to these lines in VHDL:
process begin
wait until rising_edge(mysig) for 1 us;
if rising_edge(mysig) do_something() else do_something_else(); end if;
...
- 940
0
votes
1
answer
184
views
Difference between `typedef` and `localparam type` in SystemVerilog
In SystemVerilog, to create a custom type based on another type I believe I can use either typedef or localparam type. For example, I believe the following are equivalent:
typedef logic [31:0] T;
...
- 464
1
vote
1
answer
75
views
Unexpected Waveform Behavior During RAM Data Transfer
I currently need to read 128 8-bit data. After reading 128 data, they are combined into a 1024-bit RAM which is then assigned to dout. The ram_cnt will count from 0 to 65535. When it counts 128 (0~...
- 27
1
vote
2
answers
86
views
Is there a formal statement in the IEEE SystemVerilog standard that temporary variables can be used in procedural blocks?
I wrote a module which used the writing method like:
always_ff@(posedge clk)begin
logic [WIDTH-1:0] signal1;
........
end
When I compiled it in VCS, I drove the signal in testbench, and when I ...
- 13
1
vote
1
answer
807
views
RAM array displays 'XXXXX'
Purpose: Input 128 data, store them in RAM, and output them to dout after collecting 128 data.
di is an input variable. RAM is used to store 128 data. When RAM collects 128 numbers, dout will write ...
- 13
3
votes
1
answer
125
views
Verilog full adder
This is the Verilog question. I have written the code according to the image, but I'm getting mismatch in the output, can I get some assistance?
module add1 ( input a, input b, input cin, output ...
- 73
1
vote
1
answer
108
views
How to get my 4:1 multiplexer outputs right when implementing a function?
I've been assigned to create a 4:1 multiplexer in Verilog, and then implement the function:
F(X, Y, Z) = (X*Y') + (Y'*Z') + (X'*Z')
If I did the everything right on paper, the s0 = Y, s1 = Z, I0 = 0, ...
- 11
-1
votes
1
answer
82
views
Intel FGPA ModelSim Error: Invalid time string
I have been working on my desktop using Quartus prime lite and ModelSim, but recently I got a weird error that I can't seem to fix. I have tried restarting my pc, uninstalling and reinstalling Quartus ...
- 1
0
votes
1
answer
1k
views
Vivado 2024.1 – Warning: [Synth 8-7080] Parallel synthesis criteria is not met – what does it mean and how to resolve it?
I'm using Vivado 2024.1 with full-project synthesis (not out-of-context), and I’m getting this warning during synthesis:
[Synth 8-7080] Parallel synthesis criteria is not met
The design builds and ...
- 6,769
1
vote
1
answer
87
views
No expected result when using Vivado. What's the problem with the testbench file?
I tried to reproduce loadable counter in Vivado 2023.1, but I cannot get expected result.
My testbench file is below:
`timescale 1ns / 1ps
module behav_counter();
reg [7:0] d;
reg clk;
reg ...
- 2,511
1
vote
1
answer
130
views
Ternary operator or always_comb with if in SystemVerilog
Suppose I have a module that takes in two numbers and a signal telling either it is signed multiplication or unsigned. Module has to multiply.
module signed_or_unsigned_mul
# (
parameter n = 8
)
(
...
1
vote
1
answer
97
views
In a testbench, is there a way to see the internal declared regs/wires of a module without having to connect them to ports?
Let's say we're trying to write a Verilog/SystemVerilog testbench code named SC_TB for module sample_code. Is there a more practical way of seeing what reg B and wire Cw is doing in testbench, without ...
- 13
1
vote
1
answer
68
views
How to Fix “Net Cannot Be Assigned More Than One Value” Error When Using Multiple SPI Modules? [closed]
I'm working on a Verilog project for the DE10-Lite FPGA board that interfaces with a 3-axis accelerometer over SPI. I have separate SPI modules (spi_ee_config) for each axis: x_info, y_info, and ...
2
votes
1
answer
76
views
How do SystemVerilog VPI applications schedule in the Re-Active regions?
The SystemVerilog spec describes a scheduler model in Figure 4-1 (p. 67 of IEEE 1800-2023). It describes a number of regions, including an Active region set and a Re-Active region set.
Orthogonally, ...
- 53
2
votes
2
answers
110
views
What are the differences between using hierarchical names and port declarations?
In Verilog, you can declare wires/registers
as ports and connect them at instantiation (port_A in example)
as ports and connect them "later"/"outside" using hierarchical names (...
- 4,313
0
votes
1
answer
120
views
How to add ignore_bins for coverpoint which is defined in base class
How should I add ignore_bin in child class for a coverpoint which is defiened in base class?
I tried extending base covergroup but it shows compilation errors for keyword extend in this context ...
- 1
1
vote
1
answer
64
views
Use different clocks in the property from the sample clock
I need to write a property to check the divisor of a fast clock. I’ve tried the following options:
property clk_frequency_P(logic pll_clk, logic destination_clk, logic clk_en, logic reset, int divisor)...
- 153
1
vote
1
answer
343
views
Why is my waveform not showing on Vivado?
module DCP_21(
input a,
input b,
output w,
output x,
output y,
output z
);
assign w = ~(a & b);
assign x = ~(a | b);
assign y = a^b;
assign z = ~(...
- 11
1
vote
1
answer
101
views
Using Quartus IP Catalog, how can I get predefined module name and ports order?
For the code below, I utilized a predefined RAM module from Quartus to create the RAM. How do I determine the port order when instantiating it?
I understand it must be compatible with the module from ...
- 11
0
votes
1
answer
59
views
Is using ref as direction type for get task for the mailbox have intended usage here?
In SystemVerilog LRM 1800-2017 , section 15.4.5., the declaration of the get task for mailbox is the following:
task get( ref singular message );
Why is the direction type ref, not output?
0
votes
1
answer
187
views
CocoTB: How to test interaction between two Verilog modules
What is a good way to test the interaction between two (or more) modules using cocotb?
For example, say we have a transmitter (TX) and receiver (RX) module, and we want to test them together (e.g., RX ...
- 29
0
votes
1
answer
122
views
What is the difference between ##1 and |=> in System Verilog assertions and if statement vs assert statement?
Are there major differences between using ##1 and |=> in System Verilog assertions
A ##1 B and A => B. When do they behave similarly, and when do they differ? For example
property p_a_then_b;
...
- 469
0
votes
1
answer
90
views
How to write a part select expression using shift operator in system verilog?
How to write a part select expression using shift operator in system Verilog?
Given a memory word
logic [0:8] memword;
How to write the part select expression memword[i:j] in shift operator? If not ...
1
vote
1
answer
92
views
Why does carry disappear in addition?
I have the following code:
logic [3:0] a = 4'1010;
logic [3:0] b = 4'b0111;
logic [3:0] f = 4'b1000; // ~b
logic [4:0] c;
logic [4:0] d;
logic [4:0] e;
assign c = a + b; // this gives a ...
- 135
-2
votes
1
answer
147
views
FSM stuck at one state
I am developing an FSM to latch on to incoming data and compute its average in Verilog, but my FSM seems to be just stuck at one state.
Although the simulation shows it shifted perfectly in previous ...
- 21
1
vote
1
answer
150
views
Why does APB testbench not send data into the prdata register?
Here is my code on EDA Playground.
`include "uvm_macros.svh"
import uvm_pkg::*;
//////////////////////transaction class//////////////////////
class transaction extends uvm_sequence_item;
`...
- 13
-1
votes
1
answer
83
views
Anonymous struct export to top [closed]
I have an input SystemVerilog RTL like this :
typedef struct packed {
logic [1:0][3:0] a;
struct packed {
logic [4:0] b;
logic c;
logic [1:0] d;
} e; // anonymous packed struct ...
- 45